Verilog常见必备面试题
1、U verilog hdl to implement a flip-flop with synchronous RESET and SET, a Flip-flop with asynchronous RESET and SET.
always@(podge clk or negedge ret or podge t) begin if(t) Q<> el if(!ret) Q<> el Q<> end | always@(podge clk) begin 医院中午休息吗if(t) Q<> el if(!ret) Q<> el Q<> end |
异步ret和t | 同步ret和t |
| |
2、U verilog hdl to implement a latch with asynchronous RESET and SET.
always @(clk or ret or t)冰箱调温度
begin
if(t)
Q=1;
el if(!ret)
Q=0;
el
Q=D;
end
3、U Verilog hdl to implement a 2-to-1multiplexer.
assign Y=(SEL==1'b0)?A:B;
4、U AND gate, OR gate and Inverter toimplement a 2-to-1 multiplexer.
module MUX21(A, B, SEL, Y);
input A,B,SEL;
output Y;
net SEL_NOT, A_AND, B_AND;
not u0(SEL_NOT, SEL);
and u1(A_AND, SEL_NOT, A);
and u2(B_AND, SEL, B);
or u3(Y, A_AND, B_AND);
endmodule
5、U a 2-to-1 multiplexer to implement a two input OR gate.
module or2(A, B, Y);
input A, B;
output Y;
MUX21 u0(Y, A, B, B );
endmodule
module MUX21(Y, A ,B, SEL)
input A,B,SEL;
output Y;
assign Y=(SEL==1’b0):A:B;
endmodule
assign Y=A?A:B;
6、U a tri-state buffer to implement Open-Drain buffer.
assign Y=EN?DataIn:1'bz;
7、To divide one input clock by3, Written by verilog hdl.
module clk_div_3(clk, ret, clk_out);
input ret,clk;
output clk_out;
中秋节作文300字reg clk_out;
reg [1:0] cnt;
always@(podge clk or negedge ret)
begin
if(!ret)
begin cnt<>
clk_out<>
el if(cnt==2'b01) begin clk_out<>
cnt<=cnt+1'b1;>=cnt+1'b1;>
el if(cnt==2'b10) begin clk_out<>
cnt<>
el cnt<>
end
endmodule
， 占空比1/3
8、To divide one input clock by3, 50% dutycycle is required. Written by verilog hdl.
假期安排module clk_div_3(clk, ret, clk_out);
input ret,clk;
output clk_out;
reg clk_out1, clk_out2;
reg [1:0] cnt1,cnt2;
assign clk_out = clk_out1 | clk_out2;
always@(podge clk or negedge ret)
begin
if(!ret)
begin cnt1<>
clk_out1<>
el if(cnt1==2'b01) begin clk_out1<>
cnt1<=cnt1+1'b1;>=cnt1+1'b1;>
el if(cnt1==2'b10) begin clk_out1<>
cnt1<>
el cnt1<>共青团员年龄
end
always@(negedge clk or negedge ret)
begin
if(!ret)
begin cnt2<>
clk_out2<>
el if(cnt2==2'b01) begin clk_out2<>
cnt2<=cnt2+1'b1;>=cnt2+1'b1;>
el if(cnt2==2'b10) begin clk_out2<>
cnt2<>
el cnt2<>
浪漫的事end
endmodule
module clk_div_3(clk, ret, clk_out);如何种黄豆
input ret,clk;
output clk_out;
reg [1:0] cnt;
reg clk_out1, clk_out2;
always@(podge clk)
begin
if(!ret)
cnt<>
el if(cnt=='d2)
cnt<>
el
cnt<>
end
always @(podge clk or negedge ret)
begin
if(!ret)
clk_out1<>
el if(cnt=='d2)
clk_out1<>
el if(cnt == 'd1)
clk_out1<>
end
always @(negedge clk or negedge ret)
begin
巴金作品if(!ret)
clk_out2<>
el if(cnt=='d2)
clk_out2<>
el if(cnt == 'd1)
