REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its u, nor for any infringements of patents or other rights of third parties which may result from its u. No licen is granted by implication or otherwi under any patent or patent rights of Analog Devices.
a
AD7707
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700World Wide Web Site: Fax: 781/326-8703© Analog Devices, Inc., 2000
3 V/5 V, ؎10 V Input Range, 1 mW 3-Channel 16-Bit, Sigma-Delta ADC
FUNCTIONAL BLOCK DIAGRAM
AV
DRDY RESET
DIN DOUT
思想上的不足CS SCLK DV FEATURES
Charge Balancing ADC
16 Bits No Missing Codes 0.003% Nonlinearity
High Level (؎10 V) and Low Level (؎10 mV) Input Channels
True Bipolar ؎100 mV Capability on Low Level Input Channels Without Requiring Charge Pumps Programmable Gain Front End Gains from 1 to 128
Three-Wire Serial Interface
SPI™, QSPI™, MICROWIRE™ and DSP Compatible Schmitt Trigger Input on SCLK Ability to Buffer the Analog Input
2.7 V to
3.3 V or
4.75 V to
5.25 V Operation Power Dissipation 1 mW max @ 3␣V Standby Current 8 A max
20-Lead SOIC and TSSOP Packages GENERAL DESCRIPTION
The AD7707 is a complete analog front end for low frequency measurement applications. This three-channel device can accept either low level input signals directly from a transducer or high level (±10
V) signals and produce a rial digital output. It employs a sigma-delta conversion technique to realize up to 16bits of no missing codes performance. The lected input signal is applied to a proprietary programmable gain front end bad around an analog modulator. The modulator output is procesd by an on-chip digital filter. The first notch of this digital filter can be programmed via an on-chip control register allowing adjustment of the filter cutoff and output update rate.The AD7707 operates from a single 2.7 V to 3.3 V or 4.75 V to 5.25 V supply. The AD7707 features two low level pudo-differential analog input channels, one high level input channel and a differential reference input. Input signal ranges of 0mV to +20mV through 0V to +2.5V can be accommodated on both low level input channels when operating with a V DD of 5 V and a reference of 2.5 V. They can also handle bipolar input signal ranges of ±20mV through ±2.5V, which are referenced to the LCOM input. The AD7707, with a 3V supply and a 1.225V reference, can handle unipolar input signal ranges of 0mV to +10mV through 0V to +1.225V. Its bipolar input signal ranges are ±10mV through ±1.225V.
The high level input channel can accept input signal ranges of ±10V, ±5V, 0V to +10V and 0V to +5V. The AD7707 thus performs all signal conditioning and conversion for a three-channel system.
The AD7707 is ideal for u in smart, microcontroller or DSP-bad systems. It features a rial interface that can be config-ured for three-wire operation. Gain ttings, signal polarity and update ra
te lection can be configured in software using the input rial port. The part contains lf-calibration and system calibration options to eliminate gain and offt errors on the part itlf or in the system.
CMOS construction ensures very low power dissipation, and the power-down mode reduces the standby power consumption to 20␣µW typ. The parts are available in a 20-lead wide body (0.3inch) small outline (SOIC) package and a low profile 20-lead TSSOP.
PRODUCT HIGHLIGHTS
1.The AD7707 consumes less than 1 mW at 3 V supplies and 1␣MHz master clock, making it ideal for u in low power systems. Standby current is less than 8␣µA.
2.On-chip thin-film resistors allow ±10V, ±5V, 0V to +10V and 0V to +5V high level input signals to be directly accom-modated on the analog inputs without requiring split supplies or charge-pumps.
3.The low level input channels allow the AD7707 to accept input signals directly from a strain gage or transducer remov-ing a considerable amount of signal conditioning.
4.The part features excellent static performance specifications with 16 bits, no missing codes, ±0.00
3% accuracy and low rms noi. Endpoint errors and the effects of temperature drift are eliminated by on-chip calibration options, which remove zero-scale and full-scale errors.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. A
–2–AD7707–SPECIFICATIONS
Parameter
B Version 1
Units
Conditions/Comments
STATIC PERFORMANCE
Low Level Input Channels (AIN1 and AIN2)No Missing Codes 16
Bits min Guaranteed by Design. Filter Notch < 60 Hz Output Noi
See Tables I and III Depends on Filter Cutoffs and Selected Gain Integral Nonlinearity 2±0.003% of FSR max Filter Notch < 60␣Hz. Typically ±0.0003%
Unipolar Offt Error See Note 3Unipolar Offt Drift 40.5
µV/°C typ Bipolar Zero Error See Note 3Bipolar Zero Drift 40.5µV/°C typ For Gains 1, 2 and 4
0.1
µV/°C typ For Gains 8, 16, 32, 64 and 128
Positive Full-Scale Error 5See Note 3Full-Scale Drift 4, 60.5
µV/°C typ Gain Error 7See Note 3Gain Drift 4, 8
0.5ppm of FSR/°C typ Bipolar Negative Full-Scale Error 2±0.003% of FSR max Typically ±0.0007%Bipolar Negative Full-Scale Drift 4
1µV/°C typ For Gains of 1 to 40.6
µV/°C typ For Gains of 8 to 128
HIGH LEVEL INPUT CHANNEL (AIN3)No Missing Codes 16
Bits min
Guaranteed by Design. Filter Notch < 60␣Hz Output Noi
See Tables IV and VI Depends on Filter Cutoffs and Selected Gain Integral Nonlinearity 2±0.003% of FSR max Filter Notch < 60␣Hz. Typically ±0.0003%Unipolar Offt Error 9±10mV max Typically Within ±1.5 mV Unipolar Offt Drift 4µV/°C typ Bipolar Zero Error 9±10mV max Typically Within ±1.5 mV Bipolar Zero Drift 4µV/°C typ For Gains 1, 2 and 4
1µV/°C typ For Gains 8, 16, 32, 64 and 128Gain Error ±0.2% typ
Typically Within ±0.05%
Gain Drift
0.5
ppm of FSR/°C typ Negative Full-Scale Error 2
±0.0012
% of FSR typ
LOW LEVEL ANALOG INPUTS/REFERENCE INPUTS Specifications for AIN and REF IN Unless Noted Input Common-Mode Rejection (CMR)2Low Level Input Channels, AIN1 and AIN2
AV DD = 5 V Gain = 1100dB typ Gain = 2105dB typ Gain = 4110dB typ Gain = 8 to 128130dB typ AV DD = 3 V Gain = 1105dB typ Gain = 2110dB typ Gain = 4120dB typ Gain = 8 to 128130
dB typ Normal-Mode 50 Hz Rejection
2
98dB typ For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ±0.02 × f NOTCH Normal-Mode 60 Hz Rejection 298
dB typ For Filter Notches of 10 Hz, 20 Hz, 60 Hz, ±0.02 × f NOTCH Common-Mode 50 Hz Rejection 2
150dB typ For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ±0.02 × f NOTCH Common-Mode 60 Hz Rejection 2150
dB typ
For Filter Notches of 10 Hz, 20 Hz, 60 Hz, ±0.02 × f NOTCH Absolute/Common-Mode REF IN Voltage 2
AGND to AV DD
V min to V max Absolute/Common-Mode AIN Voltage 2, 10
AGND – 100 mV
V min BUF Bit of Setup Register = 0AV DD + 30␣mV V max AGND + 50␣mV V min BUF Bit of Setup Register = 1
AV DD – 1.5␣V
V max AIN DC Input Current 2
1nA max AIN Sampling Capacitance 210
pF max BUF = 0
AIN Differential Voltage Range 11
0 to +V REF /GAIN 12
nom Unipolar Input Range (B/U Bit of Setup Register = 1)±V REF /GAIN
nom
Bipolar Input Range (B/U Bit of Setup Register = 0)AIN Input Sampling Rate, f S GAIN × f CLKIN /64
For Gains of 1 to 4f CLKIN /8
For Gains of 8 to 128
Reference Input Range
REF IN(+) – REF IN(–) Voltage 1/1.75
V min/max AV DD = 2.7V to 3.3V. V REF = 1.225V ± 1% for Specified Performance
REF IN(+) – REF IN(–) Voltage 1/3.5V min/max
AV DD = 4.75V to 5.25V. V REF = 2.5V ± 1% for Specified Performance
REF IN Input Sampling Rate, f S f CLKIN /64
±100 mV INPUT RANGE
Low Level Input Channels, (AIN1 and AIN2)Gain = 16, Unbuffered Mode INL 2
±0.003% of FSR max Filter Notch < 60 Hz
Input Common-Mode Rejection (CMR)280dB typ Power Supply Rejection (PSR)2
90dB typ乳蓟
(AV DD = DV DD = +3 V or 5 V, REF IN(+) = +1.225␣V with AV DD = 3 V and +2.5 V with AV DD = 5 V; REF␣IN(–) = GND; VBIAS = REFIN(+); MCLK IN = 2.4576␣MHz unless otherwi
noted. All specifications T MIN to T MAX unless otherwi noted.)
数列
AD7707 Parameter B Version1Units Conditions/Comments
HIGH LEVEL ANALOG INPUT CHANNEL (AIN3)AIN3 is with respect to HICOM.
AIN3 Voltage Range+10V max
–10V min
Normal Mode 50 Hz Rejection78dB typ For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ± 0.02 × f NOTCH Normal Mode 60 Hz Rejection78dB typ For Filter Notches of 10 Hz, 20 Hz, 60 Hz, ± 0.02 × f NOTCH
AIN3 Input Sampling Rate, f S GAIN × f CLKIN/64For Gains of 1 to 4
f CLKIN/8For Gains of 8 to 128
AIN3 Input Impedance227kΩ min Typically 30 kΩ±10%; Typical Resistor Tempco is –30ppm/°C AIN3 Sampling Capacitance210pF max
VBIAS Input Range0V/AV DD V min/max Typically = REFIN(+) = 2.5 V
LOGIC INPUTS
Input Current
All Inputs Except MCLK IN±1µA max Typically ±20 nA
MCLK±10µA max Typically ±2 µA
All Inputs Except SCLK and MCLK IN
V INL, Input Low Voltage0.8V max DV DD = 5 V
0.4V max DV DD = 3 V
V INH, Input High Voltage 2.0V min DV DD = 3 V and 5 V
SCLK Only (Schmitt Triggered Input)DV DD = 5 V Nominal
V T+ 1.4/3V min/V max
V T–0.8/1.4V min/V max
V T+ – V T–0.4/0.8V min/V max
SCLK Only (Schmitt Triggered Input)DV DD = 3 V Nominal
V T+1/2.5V min/V max
V T–0.4/1.1V min/V max
V T+ – V T–0.375/0.8V min/V max
MCLK IN Only DV DD = 5 V Nominal
V INL, Input Low Voltage0.8V max
V INH, Input High Voltage 3.5V min
MCLK IN Only DV DD = 3 V Nominal
V INL, Input Low Voltage0.4V max
V INH, Input High Voltage 2.5V min
LOGIC OUTPUTS (Including MCLK OUT)
V OL, Output Low Voltage0.4V max I SINK = 800␣µA Except for MCLK OUT.13 DV DD = 5 V
0.4V max I SINK = 100␣µA Except for MCLK OUT.13 DV DD = 3 V
V OH, Output High Voltage4V min I SOURCE = 200 µA Except for MCLK OUT.13 DV DD = 5 V
DV DD – 0.6V min I SOURCE = 100␣µA Except for MCLK OUT.13 DV DD = 3 V Floating State Leakage Current±10µA max
Floating State Output Capacitance149pF typ
Data Output Coding Binary Unipolar Mode
Offt Binary Bipolar Mode
SYSTEM CALIBRATION
Low Level Input Channels (AIN1 and AIN2)
Positive Full-Scale Calibration Limit15(1.05 × V REF)/GAIN V max GAIN Is The Selected PGA Gain (1 to 128)
Negative Full-Scale Calibration Limit15– (1.05 × V REF)/GAIN V max GAIN Is The Selected PGA Gain (1 to 128)
Offt Calibration Limit16– (1.05 × V REF)/GAIN V max GAIN Is The Selected PGA Gain (1 to 128)
Input Span16(0.8 × V REF)/GAIN V min GAIN Is The Selected PGA Gain (1 to 128)
(2.1 × V REF)/GAIN V max GAIN Is The Selected PGA Gain (1 to 128)
High Level Input Channels (AIN3)
Positive Full-Scale Calibration Limit15(8.4 × V REF)/GAIN V max GAIN Is The Selected PGA Gain (1 to 128)
Negative Full-Scale Calibration Limit15– (8.4 × V REF)/GAIN V max GAIN Is The Selected PGA Gain (1 to 128)
Offt Calibration Limit16– (8.4 × V REF)/GAIN V max GAIN Is The Selected PGA Gain (1 to 128)
Input Span16(6.4 × V REF)/GAIN V min GAIN Is The Selected PGA Gain (1 to 128)
(16.8 × V REF)/GAIN V max GAIN Is The Selected PGA Gain (1 to 128)
POWER REQUIREMENTS
Power Supply Voltages
AV DD Voltage+2.7 to +3.3 or
+4.75 to +5.25V For Specified Performance
DV DD Voltage+2.7 to +5.25V For Specified Performance
Power Supply Currents
AV DD Current AV DD = 3␣V or 5␣V. Gain = 1 to 4
0.27mA max Typically 0.22 mA. BUF = 0. f CLK IN = 1 MHz
or 2.4576␣MHz
0.6mA max Typically 0.45 mA. BUF = 1. f CLK IN = 1 MHz
or 2.4576 MHz
AV DD = 3V or 5␣V. Gain = 8 to 128
0.5mA max Typically 0.38␣mA. BUF = 0. f CLK IN = 2.4576␣MHz
1.1mA max Typically 0.81␣mA. BUF = 1. f CLK IN =
2.4576␣MHz
REV. A–3–
REV. A
–4–AD7707–SPECIFICATIONS
Parameter
B Version 1
Units
Conditions/Comments
POWER REQUIREMENTS (Continued)DV DD Current 17
Digital I/Ps = 0␣V or DV DD . External MCLK IN 0.080mA max Typically 0.06␣mA. DV DD = 3␣V. f CLK IN = 1␣MHz 0.15mA max Typically 0.13 mA. DV DD = 5␣V. f CLK IN = 1␣MHz
0.18mA max Typically 0.15␣mA. DV DD = 3␣V. f CLK IN = 2.4576␣MHz 0.35
mA max Typically 0.3␣mA. DV DD = 5␣V. f CLK IN = 2.4576␣MHz Power Supply Rejection 19
See Note 20
dB typ
Normal Mode Power Dissipation 17
AV DD = DV DD = +3V. Digital I/Ps = 0V or DV DD .External MCLK IN Excluding Dissipation in the AIN3Attenuator
1.05mW max Typically 0.84 mW. BUF = 0. f CLK IN = 1␣MHz, All Gains.
2.04mW max Typically 1.53 mW. BUF = 1. f CLK IN = 1␣MHz, All Gains.1.35mW max Typically 1.11 mW. BUF = 0. f CLK IN = 2.4576 MHz,Gain = 1 to 4.
2.34
mW max
Typically 1.9 mW. BUF = 1. f CLK IN = 2.4576 MHz,Gain = 1 to 4.
Normal Mode Power Dissipation 17
AV DD = DV DD = +5V. Digital I/Ps = 0␣V or DV DD .External MCLKIN
2.1mW max Typically 1.75 mW. BUF = 0. f CLK IN = 1␣MHz, All Gains.
3.75mW max Typically 2.9 mW. BUF = 1. f CLK IN = 1␣MHz, All Gains.3.1mW max Typically 2.6 mW. BUF = 0. f CLK IN = 2.4576 MHz.
4.75mW max Typically 3.75 mW. BUF = 1. f CLK IN = 2.4576 MHz.Standby (Power-Down) Current 18
18µA max External MCLK IN = 0V or DV DD . Typically 9␣µA.AV DD = +5V
8
µA max
External MCLK IN = 0V or DV DD . Typically 4␣µA.AV DD = +3V␣
NOTES
1
Temperature range as follows: B Version, –40°C to +85°C.
2
The numbers are established from characterization or design at initial product relea.3
A calibration is effectively a conversion so the errors will be of the order of the conversion noi shown in Tables I and III for the low level input channels AIN1and AIN2. This applies after calibration at the temperature of interest.4
Recalibration at any temperature will remove the drift errors.5
Positive full-scale error includes zero-scale errors (unipolar offt error or bipolar zero error) and applies to both unipolar and bipolar input ranges.6
Full-scale drift includes zero-scale drift (unipolar offt drift or bipolar zero drift) and applies to both unipolar and bipolar input ranges.7
Gain error does not include zero-scale errors. It is calculated as full-scale error–unipolar offt error for unipolar ranges and full-scale error–bipolar zero error for bipolar ranges.8
Gain error drift does not include unipolar offt drift/bipolar zero drift. It is effectively the drift of the part if zero scale calibrations only were performed.9
21世纪少年Error is removed following a system calibration.10
This common-mode voltage range is allowed provided that the input voltage on analog inputs does not go more positive than AV DD + 30 mV or go more negative than AGND – 100␣mV. Parts are functional with voltages down to AGND – 200 mV, but with incread leakage at high temperature.11
The analog input voltage range on AIN(+) is given here with respect to the voltage on LCOM on the low level input channels (AIN1 and AIN2) and is given with respect to the HCOM input on the high level input channel AIN3. The absolute voltage on the low level analog inputs should not go more positive than AV DD +100␣mV, or go more negative than GND␣– 100␣mV for specified performance. Input voltages of AGND – 200 mV can be accommodated, but with incread leakage at high temperature.12
V REF = REF IN(+) – REF IN(–).13
The logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.14
Sample tested at +25°C to ensure compliance.15
After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, the device will output all 0s.16
The calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV DD + 30␣mV or go more negative than AGND –30␣mV. The offt calibration limit applies to both the unipolar zero point and the bipolar zero point.17
When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DV DD current and power dissipation will vary depending on the crystal or resonator type (e Clocking and Oscillator Circuit ction).18
If the external master clock continues to run in standby mode, the standby current increas to 150␣µA typical at 5 V and 75 µA at 3 V. When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or resonator type (e Standby Mode ction).19
Measured at dc and applies in the lected passband. PSRR at 50␣Hz will exceed 120␣dB with filter notches of 25 Hz or 50␣Hz. PSRR at 60␣Hz will exceed 120␣dB with filter notches of 20 Hz or 60␣Hz.20
PSRR depends on both gain and AV DD .
Low Level Input Channels, AIN1 and AIN2High Level Input Channel, AIN3Gain
1248–128Gain 1
248–128AV DD = 3 V 86788593AV DD = 3 V 68606775AV DD = 5 V
90
78
84
91
AV DD
= 5 V 72
呵呵是什么意思60
66
73
Specifications subject to change without notice.
REV. A AD7707
–5–
TIMING CHARACTERISTICS
1, 2
Limit at T MIN , T MAX Parameter (B Version)Units Conditions/Comments
f CLKIN 3, 4
400kHz min Master Clock Frequency: Crystal Oscillator or Externally Supplied for 5
MHz max Specified Performance
梦鬼
t CLKIN LO 0.4 × t CLKIN ns min Master Clock Input Low Time. t CLKIN = 1/f CLKIN t CLKIN HI 0.4 × t CLKIN ns min Master Clock Input High Time t 1500 × t CLKIN ns nom DRDY High Time t 2
100ns min RESET Pulwidth
Read Operation t 30ns min DRDY to CS Setup Time
t 4120ns min CS Falling Edge to SCLK Rising Edge Setup Time t 550ns min SCLK Falling Edge to Data Valid Delay 80ns max DV DD = +5␣V 100ns max DV DD = +3.0␣V
t 6100ns min SCLK High Pulwidth t 7100ns min SCLK Low Pulwidth
t 80ns min CS Rising Edge to SCLK Rising Edge Hold Time t 96
10ns min Bus Relinquish Time after SCLK Rising Edge 60ns max DV DD = +5␣V 100ns max DV DD = +3.0␣V
t 10
100ns max SCLK Falling Edge to DRDY High 7
Write Operation t 11120ns min CS Falling Edge to SCLK Rising Edge Setup Time t 1230ns min Data Valid to SCLK Rising Edge Setup Time t 1320ns min Data Valid to SCLK Rising Edge Hold Time t 14100ns min SCLK High Pulwidth t 15100ns min SCLK Low Pulwidth
t 16
ns min
CS Rising Edge to SCLK Rising Edge Hold Time
NOTES 1单成语
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV DD ) and timed from a voltage level of 1.6 V.2
See Figures 16 and 17.3
f CLKIN Duty Cycle range is 45% to 55%. f CLKIN must be supplied whenever the AD7707 is not in Standby mode. If no clock is prent in this ca, the device can draw higher current than specified and possibly become uncalibrated.4
The AD7707 is production tested with f CLKIN at 2.4576␣MHz (1␣MHz for some I DD tests). It is guaranteed by characterization to operate at 400␣kHz.5
The numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V OL or V OH limits.6
The numbers are derived from the measured time taken by the data output to change 0.5␣V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.7
DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high, although care should be taken that subquent reads do not occur clo to the next output update.
DD = +5V DD = +3V)
DD = +5V DD = +3V)
Figure 1.Load Circuit for Access Time and Bus Relinquish Time
(AV DD = DV DD = +2.7 V TO +5.25 V, AGND = DGND = 0 V; f CLKIN = 2.4576 MHz; Input
Logic = 0, Logic 1 = DV DD unless otherwi noted.)
REV. A
AD7707
–6–CAUTION
ESD (electrostatic discharge) nsitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection.Although the AD7707 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
儿童手工剪纸
ABSOLUTE MAXIMUM RATINGS*
(T A = +25°C unless otherwi noted)
AV DD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3␣V to +7␣V AV DD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3␣V to +7␣V DV DD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3␣V to +7␣V DV DD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3␣V to +7␣V AV DD to DV DD . . . . . . . . . . . . . . . . . . . . . . . . –0.3␣V to +7 V DGND to AGND . . . . . . . . . . . . . . . . . . . . . –0.3␣V to +0.3␣V AIN1, AIN2 Input Voltage to
LOCOM . . . . . . . . . . . . . . . . . . . . –0.3 V to AV DD + 0.3␣V AIN3 Input Voltage to HICOM . . . . . . . . . . . –11 V to +30␣V VBIAS to AGND . . . . . . . . . . . . . . . . –0.3 V to AV DD + 0.3␣V HICOM, LOCOM to AGND . . . . . . –0.3 V to AV DD + 0.3␣V REF(+), REF(–) to AGND . . . . . . . . –0.3 V to AV DD + 0.3␣V Digital Input Voltage to DGND . . . . –0.3 V to DV DD + 0.3 V Digital Output Voltage to DGND . . . –0.3 V to DV DD + 0.3 V Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W Lead Temperature, Soldering
Vapor Pha (60 c) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 c) . . . . . . . . . . . . . . . . . . . . .
. . . . . +220°C TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 139°C/W Lead Temperature, Soldering
Vapor Pha (60 c) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 c) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3kV
*Stress above tho listed under Absolute Maximum Ratings may cau perma-nent damage to the device. This is a stress rating only; functional operation of the device at the or any other conditions above tho indicated in the operational ction of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
V DD
Temperature Package Package Model
Supply Range
Description Options AD7707BR 2.7 V to 5.25 V –40°C to +85°C SOIC R-20AD7707BRU
2.7 V to 5.25 V
–40°C to +85°C TSSOP
RU-20
EVAL-AD7707EB
Evaluation Board
