16-Bit 500 kSPS PulSAR®
Unipolar ADC with Reference
AD7666 Rev.0
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However, no responsibility is assumed by Analog Devices for its u, nor for any
infringements of patents or other rights of third parties that may result from its u. Specifications subject to change without notice. No licen is granted by implication or otherwi under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329. Fax: 781.326.8703© 2004 Analog Devices, Inc. All rights rerved.
FEATURES
2.5 V internal reference: typical drift 3 ppm/°C Guaranteed max drift 15 ppm/°C
Throughput: 500 kSPS
INL: ±2.0 LSB max (±0.0038% of full scale)主题班会优秀设计方案
16-bit resolution with no missing codes
S/(N+D): 88 dB min @ 20 kHz
THD: –96 dB max @ 20 kHz
Analog input voltage range: 0 V to 2.5 V
Both AC and DC specifications
No pipeline delay
Parallel and rial 5 V/3 V interface
SPI®/QSPI TM/MICROWIRE TM/DSP compatible
Single 5 V supply operation
Power dissipation
66 mW typ, 132 µW @ 1 kSPS without REF
81 mW typ with REF
48-lead LQFP and 48-lead LFCSP packages
Pin-to-pin compatible with PulSAR ADCs APPLICATIONS
Data acquisition
Medical instruments
Digital signal processing
Spectrum analysis
王菲语录Instrumentation
徐悲鸿的奔马图Battery-powered systems
Process control
GENERAL DESCRIPTION
The AD7666* is a 16-bit, 500 kSPS, charge redistribution SAR analog-to-digital converter that operates from a single 5 V power supply. The part contains a high speed, 16-bit sampling ADC, an internal conversion clock, internal reference, error correction circuits, and both rial and parallel system inter- face ports. The AD7666 is hardware factory-calibrated and comprehensively tested to ensure ac parameters such as signal-to-noi ratio (SNR) and total harmonic distortion (THD), in addition to the more traditional dc parameters of gain, offt, and linearity.
The AD7666 is available in a 48-lead LQFP and a tiny 48-lead LFCSP, with operation specified from –40°C to +85°C.
*Patent Pending.
FUNCTIONAL BLOCK DIAGRAM
3
3
4
-
-
1
眉毛运势
AVDD
AGND
IN
RESET
策划小品
PDREF
Figure 1. Functional Block Diagram
Table 1. PulSAR Selection
Type/kSPS 100–250 500–570
800–
1000 Pudo-
Differential
AD7651
AD7660/AD7661
加强党内监督
AD7650/AD7652
AD7664/AD7666
AD7653
AD7667 True Bipolar AD7663AD7665AD7671 True
Differential
AD7675AD7676AD7677 18-Bit AD7678AD7679AD7674 Multichannel/
Simultaneous
AD7654
AD7655
PRODUCT HIGHLIGHTS
1.Fast Throughput.
The AD7666 is a 500 kSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.
2.Superior INL.
The AD7666 has a maximum integral nonlinearity of
2.0 LSB with no missing 16-bit codes.
3.Internal Reference.
The AD7666 has an internal reference with a typical宅斗小说
temperature drift of 3 ppm/°C.
4.Single-Supply Operation.
The AD7666 operates from a single 5 V supply. Its power
dissipation decreas with throughput.
5.Serial or Parallel Interface.
Versatile parallel or 2-wire rial interface arrangement is compatible with both 3 V and 5 V logic.
AD7666
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TABLE OF CONTENTS
3 5 Absolute 7 7 Pin Configuration and 8 Definitions 11 Typical 12 .16 16 Typical .18 Power Dissipation 20 21 22
................................22 22 Master 23 Slave 24 26 27 Bipolar and Wider 27 Evaluating the AD7666’27 28 Ordering Guide.. (28)
REVISION HISTORY
Revision 0: Initial Version
AD7666
Rev. 0 | Page 3 of 28
SPECIFICATIONS
Table 2. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwi noted
Parameter Conditions Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range V IN – V INGND 0 V REF V Operating Input Voltage V IN –0.1 +3 V V INGND –0.1 +0.5 V Analog Input CMRR f IN = 10 kHz 65 dB Input Current 500 kSPS Throughput 7.7 µA
Input Impedance 1
THROUGHPUT SPEED Complete Cycle 2 µs Throughput Rate 0 500 kSPS DC ACCURACY Integral Linearity Error –2.0 +2.0 LSB 2 No Missing Codes 16 Bits Differential Linearity Error –1.0 +1.5 LSB Transition Noi 0.7 LSB Unipolar Zero Error, T MIN to T MAX 3 ±5 LSB Unipolar Zero Error Temperature Drift ±0.5 ppm/°C Full-Scale Error, T MIN to T MAX 3 REF = 2.5 V ±0.08 % of FSR Full-Scale Error Temperature Drift ±1.4 ppm/°C Power Supply Sensitivity AVDD = 5 V ± 5% ±2 LSB AC ACCURACY Signal-to-Noi f IN = 20 kHz 88 89.2 dB 4 Spurious Free Dynamic Range f IN = 20 kHz 96 107 dB Total Harmonic Distortion f IN = 20 kHz –106 –96 dB Signal-to-(Noi + Distortion) f IN = 20 kHz 88 89.1 dB –60 dB Input, f IN = 20 kHz 30 dB –3 dB Input Bandwidth 12 MHz SAMPLING DYNAMICS Aperture Delay 2 ns Aperture Jitter 5 ps rms
Transient Respon Full-Scale Step 750 ns REFERENCE Internal Reference Voltage V REF @ 25°C 2.493 2.5 2.507 V Internal Reference Temperature Drift –40°C to +85°C ±3 ±15 ppm/°C Output Voltage Hysteresis –40°C to +85°C 50 ppm Long Term Drift 100 ppm/1000 Hours Line Regulation AVDD = 5 V ± 5% ±15 ppm/V Turn-On Settling Time C REF = 10 µF 5 ms Temperature Pin Voltage Output @ 25°C 300 mV Temperature Sensitivity 1 mV/°C Output Resistance 4 kΩ External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V External Reference Current Drain 500 kSPS Throughput 120 µA
AD7666
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Parameter Conditions Min Typ Max Unit DIGITAL INPUTS Logic Levels V IL –0.3 +0.8 V V IH 2.0 DVDD + 0.3 V I IL –1 +1 µA I IH –1 +1 µA DIGITAL OUTPUTS
Data Format 5
Pipeline Delay 6 V OL I SINK = 1.6 mA 0.4 V V OH I SOURCE = –500 µA OVDD – 0.6 V POWER SUPPLIES Specified Performance AVDD 4.75 5 5.25 V DVDD 4.75 5 5.25 V OVDD 2.7 5.257V Operating Current 500 kSPS Throughput
AVDD 8
With Reference and Buffer 12.2 mA AVDD 9Reference and Buffer Alone 3 mA
DVDD 10
4.1 mA OVDD 10 102 µA
Power Dissipation without REF 8, 10
500 kSPS Throughput 66 75 mW 1 kSPS Throughput 132 µW
Power Dissipation with REF 8, 10
500 kSPS Throughput 81 90 mW TEMPERATURE RANGE 11 Specified Performance T MIN to T MAX –40 +85 °C
1See An ction.
alog Input 2
LSB means least significant bit. With the 0 V to 2.5 V input range, 1 LSB is 38.15 µV. 3
See the De ction. The specifications do not include the error contribution from the external reference. finitions of Specifications 4
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwi specified. 5
Parallel or Serial 16-Bit. 6
Conversion results are available immediately after completed conversion. 7
The max should be the minimum of 5.25 V and DVDD + 0.3 V. 8
With REF, PDREF and PDBUF are LOW; without REF, PDREF and PDBUF are HIGH. 9
With PDREF, PDBUF LOW and PD HIGH. 10
Tested in parallel reading mode. 11
Consult factory for extended temperature range.
AD7666 TIMING SPECIFICATIONS
抠门的人
1In rial interface mode, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C L of 10 pF; otherwi, the load is 60 pF maximum.
2In rial master read during convert mode. See Table 4 for rial master read after convert mode.
Rev. 0 | Page 5 of 28
