Dual 64-and 256-Position I2C Nonvolatile Memory Digital Potentiometers
AD5251/AD5252小手歌
Rev.0
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FEATURES
AD5251: Dual 64-position resolution
AD5252: Dual 256-position resolution
1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Nonvolatile memory1 stores wiper tting w/write protection Power-on refreshed with EEMEM ttings in 300 µs typ EEMEM rewrite time = 540 µs typ
Resistance tolerance stored in nonvolatile memory
12 extra bytes in EEMEM for ur-defined information
十字相乘法例题I2C compatible rial interface
Direct read/write access of RDAC2 and EEMEM registers Predefined linear increment/decrement co
mmands Predefined ±6 dB step change commands
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Synchronous or aysynchronous dual channel update
Wiper tting read back
4 MHz bandwidth—1 kΩ version
Single supply 2.7 V to 5.5 V
Dual supply ±2.25 V to ±2.75 V
2 slave address decoding bits allow operation of 4 devices 100-year typical data retention T A = 55°C
Operating temperature –40°C to +85°C APPLICATIONS
Mechanical potentiometer replacement
General purpo DAC replacement
LCD panel V COM adjustment White LED brightness adjustment
RF ba station power amp bias control
Programmable gain and offt control
Programmable voltage-to-current conversion Programmable power supply
Sensor calibrations
FUNDAMENTAL BLOCK DIAGRAM
3
8
2
3
-
-
包餐制1
Figure 1.
1The terms nonvolatile memory and EEMEM are ud interchangeably.
2The terms digital potentiometer and RDAC are ud interchangeably.
GENERAL DESCRIPTION
The AD5251/AD5252 are dual-channel, I2C, nonvolatile mem-ory, digitally controlled potentiometers with 64/256 positions, respectively. The devices perform the same electronic adjust-ment functions as mechanical potentiometers, trimmers, and variable resistors. The parts’ versatile programmability allows multiple modes of operation, including read/write access in the RDAC and EEMEM registers, increment/decrement of resistance, resistance changes in ±6 dB scales, wiper tting readback, and extra EEMEM for storing ur-defined infor-mation such as memory data for other components, look-up table, or system identification information.
The AD5251/AD5252 allow the host I2C controllers to write any of the 64- or 256-step wiper ttings in the RDAC registers and store them in the EEMEM. Once the ttings are stored, they are restore
d automatically to the RDAC registers at system power-on; the ttings can also be restored dynamically.
The AD5251/AD5252 provide additional increment, decrement, +6 dB step change, and –6 dB step change in synchronous or asynchronous channel update modes. The increment and decrement functions allow stepwi linear adjustments, while ±6 dB step changes are equivalent to doubling or halving the RDAC wiper tting. The functions are uful for steep-slope nonlinear adjustments such as white LED brightness and audio volume control. The parts have a patented resistance tolerance storing function which enable the ur to access the EEMEM and obtain the absolute end-to-end resistance values of the RDACs for precision applications. The AD5251/AD5252 are available in TSSOP-14 packages in 1 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ options and all parts can operate over the –40°C to +85°C extended industrial temperature range.
AD5251/AD5252
Rev.0 | Page 2 of 28
TABLE OF CONTENTS
.3 Interface 7 Absolute 8 8 Pin Configuration and .9 I 2C Interface 9 I 2C Interface 10 I 2C Interface .11 RDAC/11 I 2C Compatible 2-Wire 15 Typical 16 20 Linear Increment and 20 ±6 dB Adjustments (Doubling/Halving WIPER Setting).....20 Digital Input/21 Multiple Devices on .21 Terminal Voltage 21 Power-Up and 21 Layout and Power .22 Digital 22 Programmable
..22 Programmable 24 LCD Panel V com 24 24 Adjustable High Power 24 25 Ordering Guide.. (25)
REVISION HISTORY
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6/04—Revision 0: Initial Version
AD5251/AD5252
Rev. 0 | Page 3 of 28
ELECTRICAL CHARACTERISTICS
1 kΩ Version. V DD = 3 V ± 10% or 5 V ± 10%; V SS = 0 V or V DD /V SS = ± 2.5 V ± 10%; V A = +V DD , V B = 0 V, –40°C < T A < +85°C, unless otherwi noted. Table 1.
Parameter Symbol Conditions Min Typ 1Max Unit
DC CHARACTERISTICS
RHEOSTAT MODE
Resolution N AD5251/AD5252 6/8 Bits
Resistor Differential
Nonlinearity 2R-DNL R WB , R WA = NC, V DD = 5.5 V, AD5251 –0.5 ±0.2 +0.5 LSB R WB , R WA = NC, V DD = 5.5 V, AD5252 –1 ±0.25 +1 LSB R WB , R WA = NC, V DD = 2.7 V, AD5251 –0.75 ±0.3 +0.75 LSB R WB , R WA = NC, V DD = 2.7 V, AD5252 –1.5 ±0.3 +1.5 LSB Resistor Nonlinearity 2 R-INL R WB , R WA = NC, V DD = 5.5 V, AD5251 –0.5 ±0.2 +0.5 LSB R WB , R WA = NC, V DD = 5.5 V, AD5252 –2 ±0.5 +2 LSB R WB , R WA = NC, V DD = 2.7 V, AD5251 –1 +2.5 +4 LSB R WB , R WA = NC, V DD = 2.7 V, AD5252 –2 +9 +14 LSB Nominal Resistor Tolerance ∆R AB /R AB T A = 25°C –30 +30 % Resistance Temperature
Coefficent (∆R AB /R AB ) × 106/∆T
650 ppm/°C Wiper Resistance R W I W = 1 V/R, V DD = 5 V 75 130 Ω I W = 1 V/R, V DD = 3 V 200 300 Ω Channel Resistance Matching ∆R AB1/∆R AB3 0.15 %
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DC CHARACTERISTIC
POTENTIOMETER DIVIDER MODE Differential Nonlinearity 3DNL AD5251 –0.5 ±0.1 +0.5 LSB AD5252 –1 ±0.25 +1 LSB
Integral Nonlinearity 3
INL AD5251 –0.5 ±0.2 +0.5 LSB AD5252 –2 ±0.5 +2 LSB Voltage Divider Temperature
Coefficent (∆V W /V W ) × 106/∆T Code = half scale
25 ppm/°C Full-Scale Error V WFSE Code = full scale, V DD = 5.5 V, AD5251 –5 –3 0 LSB Code = full scale, V DD = 5.5 V, AD5252 –16 –11 0 LSB Code = full scale, V DD = 2.7 V, AD5251 −6 –4 0 LSB Code = full scale, V DD = 2.7 V, AD5252 –23 –16 0 LSB Zero-Scale Error V WZSE Code = zero scale, V DD = 5.5 V, AD5251 0 3 5 LSB Code = zero scale, V DD = 5.5 V, AD5252 0 11 16 LSB Code = zero scale, V DD = 2.7 V, AD5251 0 4 6 LSB Code = zero scale, V DD = 2.7 V, AD5252 0 15 20 LSB RESISTOR TERMINALS Voltage Range 4V A , V B , V W V SS V DD V
Capacitance 5
Ax, Bx C A , C B f = 1 kHz, measured to GND,
Code = half scale
85 pF Capacitance 5
Wx C W f = 1 kHz, measured to GND,
Code = half scale
95 pF Common-Mode Leakage
Current I CM
V A = V B = V DD /2 0.01 1 µA DIGITAL INPUTS and OUTPUTS Input Logic High V IH V DD = 5 V, V SS = 0 V 2.4 V V DD /V SS = 2.7 V/0 V or V DD /V SS = ± 2.5 V 2.1 V Input Logic Low V IL V DD = 5V, V SS = 0 V 0.8 V Output Logic High (SDA) V OH R PULL-UP = 2.2 kΩ to V DD = 5 V, V SS = 0 V 4.9 V Output Logic Low (SDA) V OL R PULL-UP = 2.2 kΩ to V DD =5 V, V SS = 0 V 0.4 V
AD5251/AD5252
1 Typical reprents the average reading at 25°C and V DD = 5 V.
马开集团2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD52521 kΩ version at V DD = 2.7 V, I W = V DD/R for both V DD =
3 V or V DD = 5 V.
3 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = V DD and V B = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
4 Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.
5 Guaranteed by design and not subject to production test.
6 cmd 0 NOP should be activated after cmd 1 to minimize I DD_READ current consumption.
7 P DISS is calculated from I DD × V DD = 5 V.
8 All dynamic characteristics u V DD = 5 V.
Rev. 0 | Page 4 of 28
AD5251/AD5252 10 kΩ, 50 kΩ, 100 kΩ Versions. V DD = +3 V ± 10% or + 5 V ± 10%. V SS = 0 V or V DD/V SS = ± 2.5 V ± 10%. V A = +V DD, V B = 0 V,
–40°C < T A < +85°C, unless otherwi noted.
Rev. 0 | Page 5 of 28
AD5251/AD5252
1 Typical reprents the average reading at 25°C and V DD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD52521 kΩ version at V DD = 2.7 V, I W = V DD/R for both V DD =
笔记本电脑怎么截图快捷键3 V or V DD = 5 V.
3 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = V DD and V B = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
4 Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.
5 Guaranteed by design and not subject to production test.
6 cmd 0 NOP should be activated after cmd 1 to minimize I DD_READ current consumption.
7 P DISS is calculated from I DD × V DD = 5 V.
8 All dynamic characteristics u V DD = 5 V.
Rev. 0 | Page 6 of 28
