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Preliminary Technical Data
AD9754
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,U.S.A Tel: 781/329-4700World Wide Web Site: Fax: 781/326-8703© Analog Devices, Inc., 1998
P R E L I M I N A R Y T E C H N I C A L D A T A
14-Bit, 100 MSPS+TxDAC ®
D/A Converter
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 14-Bit Resolution
Excellent SFDR and IMD
Differential Current Outputs:2 mA to 20 mA Power Dissipation:220 mW @ 5V Power-Down Mode:25 mW @ 5V On-Chip 1.20 V Reference骄奢淫逸
CMOS-Compatible +2.7 V to +5 V Digital Interface Package:28-Lead SOIC, TSSOP Packages Edge-Triggered Latches
APPLICATIONS
Communication Transmit Channel:Ba Stations
ADSL/HFC Modems Instrumentation
PRODUCT DESCRIPTION
The AD9754 is a 14-bit resolution cond generation member of the TxDAC ries of high performance, low power CMOS digital-to-analog converters (DACs). The TxDAC family, which consists of pin compatible 8-, 10-, 12- and 14-bit DACs, is specifically optimized for the transmit signal path of communi-cation systems. All of the devices share the same interface op-tions, small outline package and pinout, providing an upward or downward component lection path bad on performance,resolution and cost. The AD9754 offers exceptional ac and dc performance while supporting update rates up to 125 MSPS.The AD9754’s flexible single-supply operating range of +4.5 V to +5.5 V and low power dissipation are well suited for portable and low power applications. Its power dissipation can be further reduced to a mere 65 mW with a slight degradation in performance by lowering the full-scale current output. Also, a power-down mode reduces the standby power dissipation to approximately 25mW.
The AD9754 is manufactured on an advanced CMOS process.A gmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Edge-triggered input latches and a 1.2 V temperature compensated bandgap reference have been integrated to provide a complete monolithic DAC solu-tion. The digital inputs support +2.7 V and +5 V CMOS logic families.
The AD9754 is a current-output DAC with a nominal full-scale output current of 20 mA and > 100 k Ω output impedance.
TxDAC is a registered trademark of Analog Devices, Inc.
Differential current outputs are provided to support single-ended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a differential output configuration. The current outputs may be tied directly to an output resistor to provide two complemen-tary, single-ended voltage outputs or fed directly into a trans-former. The output voltage compliance range is 1.25V.
The on-chip reference and control amplifier are configured for maximum accuracy and flexibility. The AD9754 can be driven by the on-chip reference or by a variety of external reference voltages. The internal control amplifier, which provides a wide (>10:1) adjustment span, allows the AD9754 full-scale current to be adjusted over a 2mA to 20 mA range while maintaining excellent dynamic performance. Thus, the AD9754 may operate at reduced power levels or be adjusted over a 20dB range to provide additional gain ranging capabilities.
The AD9754 is available in 28-lead SOIC and TSSOP packages.It is specified for operation over the industrial temperature range.
PRODUCT HIGHLIGHTS
1.The AD9754 is a member of the TxDAC product family that provides an upward or downward component lection path bad on resolution (8 to 14 bits), performance and cost.
2.Manufactured on a CMOS process, the AD9754 us a pro-prietary switching technique that enhances dynamic perfor-mance beyond that previously attainable by higher power/cost bipolar or BiCMOS devices.
3.On-chip, edge-triggered input CMOS latches readily interface to +2.7 V to +5 V CMOS logic families. The AD9754 can support update rates up to 125 MSPS.
4.A flexible single-supply operating range of +4.5V to +
一的英语怎么写5.5 V,and a wide full-scale current adjustment span of 2mA to 20 mA, allows the AD9754 to operate at reduced power levels.5.The current output(s) of the AD9754 can be easily config-ured for various single-ended or differential circuit topologies.
P R E L I M I N A R Y T E C H N I C A L D A T A
DC SPECIFICATIONS Parameter Min Typ Max Units RESOLUTION
14
Bits
DC ACCURACY 1
Integral Linearity Error (INL)T A = +25°C –1.5±1.0+1.5LSB T MIN to T MAX
–2.0+2.0LSB Differential Nonlinearity (DNL)T A = +25°C –1.5±1.0中医执业范围
+1.5LSB T MIN to T MAX
–2.0+2.0LSB ANALOG OUTPUT Offt Error
–0.025+0.025% of FSR Gain Error (Without Internal Reference)–10±2+10% of FSR Gain Error (With Internal Reference)–10±1+10% of FSR Full-Scale Output Current 2 2.020.0mA Output Compliance Range –1.0
1.25
V Output Resistance 100k ΩOutput Capacitance 5
pF REFERENCE OUTPUT Reference Voltage
1.08
1.20 1.32
V Reference Output Current 3100
nA REFERENCE INPUT Input Compliance Range 0.1
1.25
V Reference Input Resistance 1M ΩSmall Signal Bandwidth
0.5MHz
TEMPERATURE COEFFICIENTS Offt Drift
0ppm of FSR/°C Gain Drift (Without Internal Reference)±50ppm of FSR/°C Gain Drift (With Internal Reference)±100ppm of FSR/°C Reference Voltage Drift
±50
ppm/°C
POWER SUPPLY Supply Voltages AVDD 4.5 5.0 5.5V DVDD
2.7
5.0 5.5V Analog Supply Current (I AVDD )3540mA Digital Supply Current (I DVDD )4
1.52mA Supply Current Sleep Mode (I AVDD )
5.08.5mA Power Dissipation 4 (5 V, I OUTFS = 20 mA)185230mW Power Dissipation 5 (5 V, I OUTFS = 20 mA)190
mW
Power Supply Rejection Ratio 6—AVDD –0.4+0.4% of FSR/V Power Supply Rejection Ratio 6—DVDD –0.05+0.05% of FSR/V OPERATING RANGE
–40
+85
°C
NOTES 1
Measured at IOUTA, driving a virtual ground.2
Nominal full-scale current, I OUTFS , is 32 × the I REF current.3
U an external buffer amplifier to drive any external load.4
Measured at f CLOCK = 25 MSPS and f OUT = 1.0 MHz.5
Measured as unbuffered voltage output with I OUTFS = 20 mA and 50 Ω R LOAD at IOUTA and IOUTB, f CLOCK = 100 MSPS and f OUT = 40 MHz.6
±5% Power supply variation.
Specifications subject to change without notice.
(T
MIN to T MAX , AVDD = +5 V, DVDD = +5 V, I OUTFS = 20 mA, unless otherwi noted)
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AD9754–SPECIFICATIONS
P R E L I M I N A R Y T E C H N I C A L D A T A
DYNAMIC SPECIFICATIONS
Parameter
Min Typ Max
Units DYNAMIC PERFORMANCE
Maximum Output Update Rate (f CLOCK )100
125MSPS Output Settling Time (t ST ) (to 0.1%)135ns Output Propagation Delay (t PD )1ns Glitch Impul
5pV-s Output Ri Time (10% to 90%)1 2.5ns Output Fall Time (10% to 90%)1 2.5ns
Output Noi (I OUTFS = 20 mA)50pA/√Hz Output Noi (I OUTFS = 2 mA)
30
pA/√Hz
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist f CLOCK = 25 MSPS; f OUT = 1.00 MHz 0 dBFS Output T A = +25°C 8086dBc T MIN to T MAX 76
dBc –6 dBFS Output 87dBc –12 dBFS Output 80dBc –18 dBFS Output
74dBc f CLOCK = 50 MSPS; f OUT = 1.00 MHz 84dBc f CLOCK = 50 MSPS; f OUT = 2.51 MHz 80dBc f CLOCK = 50 MSPS; f OUT = 5.02 MHz 76dBc f CLOCK = 50 MSPS; f OUT = 20.2 MHz
65dBc Spurious-Free Dynamic Range within a Window
f CLOCK = 25 MSPS; f OUT = 1.00 MHz; 2 MHz Span T A = +25°C 78
86dBc T MIN to T MAX
76
dBc f CLOCK = 50 MSPS; f OUT = 5.02 MHz; 2 MHz Span 86dBc f CLOCK = 100 MSPS; f OUT = 5.04 MHz; 4 MHz Span 86dBc Total Harmonic Distortion
f CLOCK = 25 MSPS; f OUT = 1.00 MHz T A = +25°C –82–78dBc T MIN to T MAX
–74
dBc f CLOCK = 50 MHz; f OUT = 2.00 MHz –78dBc f CLOCK = 100 MHz; f OUT = 2.00 MHz
–78dBc Multitone Power Ratio (8 Tones at 110 kHz Spacing)f CLOCK = 20 MSPS; f OUT = 2.00 MHz to 2.99 MHz 0 dBFS Output 75dBFS –6 dBFS Output 84dBFS –12 dBFS Output 87dBFS –18 dBFS Output
88
dBFS青蛙青蛙
NOTES 1
Measured single-ended into 50Ω load.Specifications subject to change without notice.
(T MIN to T MAX , AVDD = +5 V, DVDD = +5 V, I OUTFS = 20 mA, Differential Transformer Coupled Output,50⍀ Doubly Terminated, unless otherwi noted)
AD9754
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AD9754
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P R E L
T E C H N I C D A T A
ABSOLUTE MAXIMUM RATINGS*
With
Parameter
Respect to Min Max Units
AVDD ACOM –0.3+6.5V DVDD DCOM –0.3+6.5V ACOM DCOM –0.3+0.3V AVDD
DVDD –6.5+6.5
V CLOCK, SLEEP DCOM –0.3DVDD + 0.3V Digital Inputs DCOM –0.3DVDD + 0.3V IOUTA, IOUTB ACOM –1.0AVDD + 0.3V ICOMP
ACOM –0.3AVDD + 0.3V REFIO, FSADJ ACOM –0.3AVDD + 0.3V REFLO
ACOM
–0.3+0.3V Junction Temperature +150°C Storage Temperature –65
+150°C Lead Temperature (10 c)
+300
°C
*Stress above tho listed under Absolute Maximum Ratings may cau perma-nent damage to the device. This is a stress rating only; functional operation of the device at the or any other conditions above tho indicated in the operational ctions of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
ORDERING GUIDE
Temperature Package Package Model
Range
Description
Options*
AD9754AR –40°C to +85°C 28-Lead 300 Mil SOIC R-28AD9754ARU –40°C to +85°C 28-Lead TSSOP RU-28AD9754-EB Evaluation Board
*R = Small Outline IC; RU = Thin Shrink Small Outline Package.
THERMAL CHARACTERISTICS Thermal Resistance
28-Lead 300 Mil SOIC θJA = 71.4°C/W θJC = 23°C/W 28-Lead TSSOP θJA = 120°C/W θJC = 40°C/W
CAUTION
ESD (electrostatic discharge) nsitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection.Although the AD9754 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
(T
MIN to T MAX , AVDD = +5 V, DVDD = +5 V, I OUTFS = 20 mA unless otherwi noted)
DIGITAL SPECIFICATIONS Parameter
Min Typ Max Units DIGITAL INPUTS
Logic “1” Voltage @ DVDD = +5 V 3.55V Logic “1” Voltage @ DVDD = +3 V 2.13V Logic “0” Voltage @ DVDD = +5 V 0 1.3V Logic “0” Voltage @ DVDD = +3 V 00.9V Logic “1” Current –10+10µA Logic “0” Current –10
+10
µA Input Capacitance 5
pF Input Setup Time (t S ) 2.0ns Input Hold Time (t H ) 1.5ns Latch Pulwidth (t LPW )
3.5
ns
Specifications subject to change without notice.
DB0–DB11
CLOCK
IOUTA
OR IOUTB
Figure 1. Timing Diagram
AD9754
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P R E L I M I N A R Y T E C H N I C A L D A T A
PIN CONFIGURATION
NC = NO CONNECT
(MSB) DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1(LSB) DB0CLOCK DVDD DCOM NC
AVDD
首开头的成语ICOMP IOUTA IOUTB ACOM NC FS ADJ REFIO REFLO SLEEP
PIN FUNCTION DESCRIPTIONS
Pin No.Name Description
生脉饮的功效与作用1
DB13
Most Significant Data Bit (MSB).2–13DB12–DB1Data Bits 1–12.
14DB0Least Significant Data Bit (LSB).
15SLEEP Power-Down Control Input. Active High. Contains active pull-down circuit; it may be left unterminated if not ud.
16REFLO Reference Ground when Internal 1.2 V Reference Ud. Connect to AVDD to disable internal reference.17
REFIO
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).Requires 0.1µF capacitor to ACOM when internal reference activated.18FS ADJ Full-Scale Current Output Adjust.19, 25NC No Connect.
20ACOM Analog Common.
21IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s.22IOUTA DAC Current Output. Full-scale current when all data bits are 1s.
23ICOMP Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.24AVDD Analog Supply Voltage (+2.7 V to +5.5 V).26DCOM Digital Common.
27DVDD Digital Supply Voltage (+2.7 V to +5.5 V).
28CLOCK
Clock Input. Data latched on positive edge of clock.
AD9754
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E L I M I N A R Y I C A L DEFINITIONS O
F SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code.
Offt Error
The deviation of the output current from the ideal of zero is called offt error. For IOUTA, 0 mA outp
ut is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are t to 1s.
Gain Error
怎样种草莓The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are t to 1s minus the output when all inputs are t to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cau either output stage saturation or breakdown, resulting in nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the ambient (+25°C) value to the value at either T MIN or T MAX . For offt and gain drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies are varied over a specified range.
Settling Time
The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition.
Glitch Impul
Asymmetrical switching times in a DAC give ri to undesired output transients that are quantified by a glitch impul. It is specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion
THD is the ratio of the sum of the rms value of the first six harmonic components to the rms value of the measured output signal. It is expresd as a percentage or in decibels (dB).
Multitone Power Ratio
The spurious-free dynamic range for an output containing mul-tiple carrier tones of equal amplitude. It is measured as the
difference between the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone.
⍀ INPUT
Figure 2.Basic AC Characterization Test Setup二年级思维导图数学
