DATA SHEET
Product specification
File under Integrated Circuits, IC01February 1991
TDA1541A操场上
Stereo high performance 16-bit DAC
查询TDA1541A/N2/R1供应商
Stereo high performance 16-bit DAC
TDA1541A
FEATURES •High sound quality
•High performance: low noi and distortion, wide dynamic range
•4 × or 8× oversampling possible •Selectable two-channel input format •TTL compatible inputs.GENERAL DESCRIPTION
The TDA1541A is a stereo 16-bit digital-to-analog
converter (DAC). The ingenious design of the electronic circuit guarantees a high performance and superior sound quality. The TDA1541A is therefore extremely suitable for u in top-end hi-fi digital audio equipment such as high quality Compact Disc players or digital amplifiers.
ORDERING INFORMATION
Note
1.SOT117; SOT117-1; 1996 August 09.QUICK REFERENCE DATA EXTENDED TYPE
NUMBER PACKAGE
PINS PIN POSITION
MATERIAL CODE TDA1541A (1)
28
DIL
plastic
SOT117
SYMBOL PARAMETER
CONDITIONS
MIN.TYP .MAX.UNIT V DD supply voltage; pin 28 4.5 5.0 5.5V −V DD1supply voltage; pin 26 4.5 5.0 5.5V −V DD2supply voltage; pin 1514.015.016.0V I DD supply current; pin 28−2740mA −I DD1supply current; pin 26−3750mA −I DD2supply current; pin 15−2535mA THD total harmonic distortion including noi −−95−90dB at 0 dB −0.00180.0032%THD total harmonic distortion including noi −−42−dB at −60 dB −0.79−%NL non-linearity
at T amb =
−20 to +85 °C −0.5 1.0LSB t cs current ttling time to ± 1LSB −0.5−µs BR input bit rate at data input;(pin 3 and 4)
−− 6.4Mbits/s f BCK clock frequency at clock input −− 6.4MHz TC FS full scale temperature coefficient at analog (AOL;AOR)−±200 ×10-6
−K -1T amb operating ambient temperature range −40−+85°C P tot
total power dissipation
−
古诗19首700
−
mW
Stereo high performance 16-bit DAC TDA1541A
(1) TDA1542.
(2) 2 ×NE5534 or equivalent.
Fig.1 Block diagram.
Stereo high performance 16-bit DAC
TDA1541A
PINNING Note
1.See Table 1data lection input.
SYMBOL PIN DESCRIPTION
LE/WS (1)1latch enable input/ word lect input BCK (1)2bit clock input
DATA L /DATA (1)3data left channel input/ data input (lected format)DATA R (1)4data right channel input GND(A)5analog ground AOR 6right channel output DECOU 7 to 13decoupling GND (D)14digital ground V DD215−15 V supply voltage COSC 16,17oscillator
巴马DECOU 18 to 24decoupling
AOL 25left channel output V DD126−5 V supply voltage OB/TWC (1)27mode lect input V DD 28
+5 V supply voltage
Fig.2 Pin configuration
海蛎子的做法FUNCTIONAL DESCRIPTION
The TDA1541A accepts input sample formats in time multiplexed mode or simultaneous mode up to 16-bit word length.The most significant bit (MSB) must always be first. The flexible input data format allows easy interfacing with signal processing chips such as interpolation filters, error correction circuits, pul code modulation adaptors and audio signal processors (ASP).
The high maximum input bit-rate and fast tting facilitates application in 8× oversampling systems
桥本一(44.1kHz to 352.8kHz or 48kHz to 384kHz) with the associated simple analog filtering function (low order, linear pha filter).
Input data lection (e also Table 1)
With the input OB/TWC connected to ground, data input (offt binary format) must be in time multiplexed mode. It is accompanied with a word lect (WS) and a bit clock input (BCK) signal. The converted samples appear at the output,at the first positive going transition of the bit clock signal after a negative going transition of the word lect signal.With OB/TWC connected to V DD the mode is the same but the data format must be in the two’s complement.
When input OB/TWC input is connected to V DD1 the two channels of data (L/R) are input simultaneously via DATA L and DATA R, accompanied with BCK and a latch-enable input (LE). With this mode lected the data must be in offt binary.The converted samples appear at the output at the positive going transition of the latch enable signal.The format of the data input signals is shown in Fig.5 and 6.
Stereo high performance 16-bit DAC TDA1541A True 16-bit performance is achieved by each channel using three 2-bit active dividers, operating on the dynamic element matching principle, in combination with a 10-bit passive current divider, bad on emitter scaling. All digital inputs are TTL compatible.
Table 1Input data lection
OB/TWC MODE PIN1PIN2PIN3PIN4
−5V simultaneous LE BCK DATA L DATA R
0V time MUX OB WS BCK DATA OB not ud
+5V time MUX TWC WS BCK DATA TWC not ud
Where:
LE= latch enable
WS= word lect,
LOW = left channel;
HIGH = right channel
BCK= bit clock
DATA L= data left
DATA R= data right
DATA OB = data offt binary
DATA TWC= data two’s complement
MUX OB= mulitplexed offt binary
MUX TWC= multiplexed two’s
嘴唇干complement = I2S- format
LIMITING VALUES
In accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN.MAX.UNIT
V DD supply voltage; pin 2807V
减费让利−V DD1supply voltage; pin 2607V
−V DD2supply voltage; pin 15017V
T stg storage temperature range−55+150°C
T amb operating ambient temperature range−40+85°C
V es electrostatic handling*−1000+1000V
外脚手架搭设规范
* Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ ries resistor.
THERMAL RESISTANCE
SYMBOL PARAMETER TYP.UNIT
R th j-a from junction to ambient30K/W
