a
AD7663* Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
u, nor for any infringements of patents or other rights of third parties that may result from its u. No licen is granted by implication or otherwi under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/326-8703© 2003 Analog Devices, Inc. All rights rerved.
REV.B 16-Bit, 250 kSPS CMOS ADC FUNCTIONAL BLOCK DIAGRAM
OGND
OVDD
BYTESWAP
SER/PAR
D[15:0]
BUSY
CS
RD
OB/2C
FEATURES
Throughput: 250 kSPS
INL: ؎3 LSB Max (؎0.0046% of Full Scale)
16-Bit Resolution with No Missing Codes
S/(N+D): 90 dB Typ @ 100 kHz
THD: –100 dB Typ @ 100 kHz
Analog Input Voltage Ranges
Bipolar: ؎10 V, ؎5 V, ؎2.5 V
Unipolar: 0 V to 10 V, 0 V to 5 V, 0 V to 2.5 V
Both AC and DC Specifications
No Pipeline Delay
Parallel (8/16 Bits) and Serial 5 V/3 V Interface
SPI®/QSPI™/MICROWIRE™/DSP Compatible
Single 5 V Supply Operation
Power Dissipation
35 mW Typical
15 W @ 100 SPS
Power-Down Mode: 7 W Max
Package: 48-Lead Quad Flatpack (LQFP)
Package: 48-Lead Chip Scale (LFCSP)
Pin-to-Pin Compatible with the AD7660/AD7664/AD7665 APPLICATIONS
Data Acquisition
Motor Control
Communication
Instrumentation
Spectrum Analysis
Medical Instruments
Process Control
GENERAL DESCRIPTION
The AD7663 is a 16-bit, 250 kSPS, charge redistribution SAR,
analog-to-digital converter that operates from a single 5V power supply. It contains a high speed 16-bit sampling ADC, a resistor input scaler that allows various input ranges, an internal conver-sion clock, error correction circuits, and both rial and parallel system interface ports.
The AD7663 is hardware factory-calibrated and is comprehen-sively tested to ensure such ac parameters as signal-to-noi ratio (SNR) and total harmonic distortion (THD), in addition to the more traditional dc parameters of gain, offt, and linearity.
It is fabricated using Analog Devices’ high performance, 0.6micron CMOS process and is available in a 48-lead LQFP and a tiny 48-lead LFCSP with operation specified from –40°C to +85°C. *Patent pending PRODUCT HIGHLIGHTS
1.Fast Throughput
The AD7663 is a 250 kSPS charge redistribution, 16-bit
SAR ADC with various bipolar and unipolar input ranges.
2.Single-Supply Operation
The AD7663 operates from a single 5 V supply and dissipates only 35 mW typical. Its power dissipation decreas with
the throughput to, for instance, only 15 µW at a 100SPS
throughput.
It consumes 7µW maximum when in power-down.
3.Superior INL
The AD7663 has a maximum integral nonlinearity of 3LSB with no missing 16-bit code.
4.Serial or Parallel Interface
Versatile parallel (8 bits or 16 bits) or 2-wire rial interface arrangement compatible with both 3 V or 5 V logic.
PulSAR Selection
Type/kSPS100–250500–570800–1000 Pudo AD7660AD7650
Differential AD7664
True Bipolar AD7663AD7665AD7671 True Differential AD7675AD7676AD7677 18-Bit AD7678AD7679AD7674 Simultaneous/AD7654AD7655 Multichannel
AD7663–SPECIFICATIONS REV. B
–2–Parameter Conditions
Min Typ
Max
Unit RESOLUTION
16
Bits
ANALOG INPUT Voltage Range
V IND – V INGND ±4 REF, 0 V to 4 REF, ±2 REF (See Table I)Common-Mode Input Voltage V INGND
–0.1+0.5
V Analog Input CMRR f IN = 45 kHz 62
dB
Input Impedance See Table I
THROUGHPUT SPEED Complete Cycle 4µs Throughput Rate
0250kSPS DC ACCURACY
Integral Linearity Error –3+3
LSB 1No Missing Codes 16
Bits Transition Noi
0.7
LSB Bipolar Zero Error 2, T MIN to T MAX
±5 V Range –25+25LSB
Other Range
–0.06+0.06% of FSR Bipolar Full-Scale Error 2, T MIN to T MAX –0.25+0.25% of FSR Unipolar Zero Error 2, T MIN to T MAX
–0.18+0.18% of FSR Unipolar Full-Scale Error 2, T MIN to T MAX –0.38
+0.38
% of FSR Power Supply Sensitivity AVDD = 5 V ±5%
±0.1
LSB AC ACCURACY Signal-to-Noi
f IN = 10 kHz 89
90dB 3f IN = 100 kHz 90dB Spurious-Free Dynamic Range f IN = 100 kHz 100dB Total Harmonic Distortion f IN = 100 kHz –100dB Signal-to-(Noi+Distortion)f IN = 10 kHz
88.5
素描静物组合90dB f IN = 100 kHz, –60 dB Input
30dB –3 dB Input Bandwidth 800kHz SAMPLING DYNAMICS Aperture Delay 2ns Aperture Jitter
5
ps rms Transient Respon
Full-Scale Step
2.75µs REFERENCE
External Reference Voltage Range 2.3
2.5AVDD – 1.85V External Reference Current Drain 250 kSPS Throughput
50
µA
DIGITAL INPUTS Logic Levels V IL –0.3+0.8
V V IH +2.0DVDD + 0.3V I IL –1+1µA I IH –1+1µA
DIGITAL OUTPUTS Data Format Parallel or Serial 16-Bit
Pipeline Delay
Conversion Results Available Immediately
after Completed Conversion
V OL I SINK = 1.6 mA 0.4
V V OH
澳洲高中
I SOURCE = –500 µA OVDD – 0.6
V
POWER SUPPLIES Specified Performance AVDD 4.755 5.25V DVDD 4.755 5.25V OVDD
2.7
5.254V Operating Current 250 kSPS Throughput
AVDD 5mA DVDD 5 1.8mA OVDD 5
10µA Power Dissipation 6
250 kSPS Throughput 53541mW 100 SPS Throughput 515
µW In Power-Down Mode 7
7
µW
(–40؇C to +85؇C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwi noted.)
REV. B
–3–
AD7663
TIMING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Unit
Refer to Figures 11 and 12Convert Pulwidth
t 15ns Time between Conversions
t 24
µs CNVST LOW to BUSY HIGH Delay t 330ns BUSY HIGH All Modes Except in
t 4 1.25
µs Master Serial Read after Convert Mode Aperture Delay
t 52
ns End of Conversion to BUSY LOW Delay t 610
ns Conversion Time t 7 1.25
µs Acquisition Time t 8 2.75µs RESET Pulwidth
t 910
ns Refer to Figures 13, 14, 15, and 16 (Parallel Interface Modes)CNVST LOW to DATA Valid Delay t 10 1.25
µs DATA Valid to BUSY LOW Delay t 1120ns Bus Access Request to DATA Valid t 1240ns Bus Relinquish Time
t 135
15ns Refer to Figures 17 and 18 (Master Serial Interface Modes)1CS LOW to SYNC Valid Delay
t 1410ns CS LOW to Internal SCLK Valid Delay t 1510ns CS LOW to SDOUT Delay
t 1610
ns CNVST LOW to SYNC Delay (Read during Convert)t 170.5卷标
µs SYNC Asrted to SCLK First Edge Delay 2t 184ns Internal SCLK Period 2t 192540
ns Internal SCLK HIGH 2t 2015ns Internal SCLK LOW 2
t 219.5ns SDOUT Valid Setup Time 2t 22 4.5ns SDOUT Valid Hold Time 2雷伊与盖亚
t 232ns SCLK Last Edge to SYNC Delay 2t 243
ns
Parameter
Conditions Min Typ
Max Unit TEMPERATURE RANGE 8Specified Performance
T MIN to T MAX
–40
+85
°C
NOTES 1
LSB means least significant bit. With the ±5 V input range, one LSB is 152.588 µV.2
这一首歌See Definition of Specifications ction. The specifications do not include the error contribution from the external reference.3
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwi specified.4
The max should be the minimum of 5.25 V and DVDD + 0.3 V.5
Tested in Parallel Reading Mode.6
Tested with the 0 V to 5 V range and V IN – V INGND = 0 V. See Power Dissipation ction.7
With OVDD below DVDD + 0.3 V and all digital inputs forced to DVDD or DGND, respectively.8
Contact factory for extended temperature range.Specifications subject to change without notice.
Table I.Analog Input Configuration
Input Voltage Input
Range IND(4R)INC(4R)INB(2R)INA(R)Impedance 1±4 REF 2V IN INGND INGND REF 5.85 k W ±2 REF V IN V IN INGND REF 3.41 k W ±REF
V IN V IN V IN
REF 2.56 k W 0 V to 4 REF V IN V IN INGND INGND 3.41 k W 0 V to 2 REF V IN V IN V IN INGND 2.56 k W 0 V to REF
V IN
V IN
V IN
V IN
Note 3
NOTES 1
Typical analog input impedance.2
With REF = 3 V, in this range, the input should be limited to –11 V to +12 V.3
For this range the input is high impedance.
(–40؇C to +85؇C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwi noted.)
REV. B
AD7663
–4–TIMING SPECIFICATIONS (continued)
Parameter
Symbol Min Typ Max Unit Refer to Figures 17 and 18 (Master Serial Interface Modes)1CS HIGH to SYNC HI-Z
t 2510ns CS HIGH to Internal SCLK HI-Z t 2610ns
伤感朋友圈CS HIGH to SDOUT HI-Z
t 2710
ns BUSY HIGH in Master Serial Read after Convert t 28See Table II µs CNVST LOW to SYNC Asrted Delay t 29 1.25µs (Master Serial Read after Convert)SYNC Deasrted to BUSY LOW Delay
t 3025
ns Refer to Figures 19 and 21 (Slave Serial Interface Modes)External SCLK Setup Time
t 315ns External SCLK Active Edge to SDOUT Delay t 32316
ns SDIN Setup Time t 335ns SDIN Hold Time
t 345ns External SCLK Period t 3525ns External SCLK HIGH t 3610ns External SCLK LOW
t 37
10
ns
NOTES 1
In rial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C L of 10 pF; otherwi, the load is 60 pF maximum.2
In Serial Master Read during Convert Mode. See Table II for Master Read after Convert Mode.Specifications subject to change without notice.
TO OUTPUT
PIN
*IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD C L OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 1.Load Circuit for Digital Interface Timing Figure 2.Voltage Reference Levels for Timing
Table II.Serial Clock Timings in Master Read after Convert
DIVSCLK[1]0011DIVSCLK[0]
0101Unit SYNC to SCLK First Edge Delay Minimum t 184202020ns Internal SCLK Period Minimum t 192550100200ns Internal SCLK Period Maximum t 194070140280ns Internal SCLK HIGH Minimum t 20152550100ns Internal SCLK LOW Minimum
t 219.5244999ns SDOUT Valid Setup Time Minimum t 22 4.5222222ns SDOUT Valid Hold Time Minimum
t 23243090ns SCLK Last Edge to SYNC Delay Minimum t 24360140300ns BUSY HIGH Width Maximum
t 28
2
2.5
3.5
5.75
µs
REV. B AD7663
–5–
PIN CONFIGURATION
ST-48 and CP-48
OB/SER/D 4/E X T /I N D 5/I N V S Y N D 6/I N V S C L D 7/R D C /S D I O G N O V D D V D D G N D 8/S D O U D 9/S C L D 10/S Y N D 11/R D E R R O C C
C C
C N
D (4R )N C (4R )N B (2R )N A (R )
N G N D
E F G N D E F
ABSOLUTE MAXIMUM RATINGS 1
Analog Inputs
IND 2, INC 2, INB 2 . . . . . . . . . . . . . . . . . . . . –11 V to +30 V INA, REF, INGND, REFGND
. . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to AVDD + 0.3 V Ground Voltage Differences
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . ±0.3 V Supply Voltages
AVDD,DVDD, OVDD . . . . . . . . . . . . . . . . –0.3 V to +7 V AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . . ±7 V DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Digital Inputs . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V Internal Power Dissipation 3 . . . . . . . . . . . . . . . . . . . 700 mW Internal Power Dissipation 4 . . . . . . . . . . . . . . . . . . . . . 2.5 W Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range
(Soldering 10c) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
1手机空间清理
Stress above tho listed under Absolute Maximum Ratings may cau perma-nent damage to the device. This is a stress rating only; functional operation of the device at the or any other conditions above tho indicated in the operational ction of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.2
See Analog Inputs ction.3
Specification is for device in free air: 48-Lead LQFP: q JA = 91°C/W, q JC = 30°C/W.4
Specification is for device in free air: 48-Lead LFCSP: q JC = 26ЊC/W.
ORDERING GUIDE
Model
Temperature Range Package Description Package Option AD7663AST –40°C to +85°C Quad Flatpack (LQFP)ST-48AD7663ASTRL –40°C to +85°C Quad Flatpack (LQFP)ST-48AD7663ACP –40ЊC to +85ЊC Chip Scale (LFCSP)CP-48AD7663ACPRL –40ЊC to +85ЊC
Chip Scale (LFCSP)CP-48
EVAL-AD7663CB 1
Evaluation Board EVAL-CONTROL BRD22
Controller Board
NOTES 1
This board can be ud as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purpos.2
This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
CAUTION
ESD (electrostatic discharge) nsitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7663 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. B
AD7663
–6–PIN FUNCTION DESCRIPTION
Pin No.Mnemonic Type Description 1AGND P Analog Power Ground Pin.
2
AVDD P
Input Analog Power Pin. Nominally 5 V.3, 6, 7,NC No Connect.
44–484BYTESWAP DI Parallel Mode Selection (8/16 Bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].5
OB/2C
DI
Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift register.
处臵
8SER/PAR DI Serial/Parallel Selection Input. When LOW, the Parallel Port is lected; when HIGH, the Serial Interface Mode is lected and some bits of the Data bus are ud as a Serial Port.
9, 10D[0:1]DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, the outputs are in high impedance.
11, 12
D[2:3] or DI/O
When SER/PAR is LOW, the outputs are ud as Bit 2 and Bit 3 of the Parallel Port Data Output Bus.
DIVSCLK[0:1]
When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the Serial Master Read after Convert Mode. The inputs, part of the Serial Port, are ud to slow down,if desired, the
internal rial clock that clocks the data output. In the other rial modes, the pins are high impedance outputs.
13
D[4]
DI/O
When SER/PAR is LOW, this output is ud as Bit 4 of the Parallel Port Data EXT/INT
When SER/PAR is HIGH, this input, part of the Serial Port, is ud as a digital lect input for choosing the internal or an external data clock, called respectively, Master and Slave Modes.With EXT/INT tied LOW, the internal clock is lected on SCLK output. With EXT/INT t to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input, and external clock is gated by CS .
14
D[5]
DI/O
When SER/PAR is LOW, this output is ud as Bit 5 of the Parallel Port Data INVSYNC When SER/PAR is HIGH, this input, part of the Serial Port, is ud to lect the active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.15D[6]
DI/O
When SER/PAR is LOW, this output is ud as Bit 6 of the Parallel Port Data INVSCLK When SER/PAR is HIGH, this input, part of the Serial Port, is ud to invert the SCLK signal.It is active in both master and slave mode.
16D[7]
DI/O
When SER/PAR is LOW, this output is ud as Bit 7 of the Parallel Port Data RDC/SDIN
When SER/PAR is HIGH, this input, part of the Serial Port, is ud as either an external data input or a read mode lection input, depending on the state of EXT/INT .
When EXT/INT is HIGH, RDC/SDIN could be ud as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read quence.When EXT/INT is LOW, RDC/SDIN is ud to lect the read mode. When RDC/SDIN is HIGH, the previous data is output on SDOUT during conversion. When RDC/SDIN is LOW,the data can be output on SDOUT only when the conversion is complete.17OGND P Input/Output Interface Digital Power Ground.
18OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface (5 V or 3 V).
19DVDD P Digital Power. Nominally at 5 V.20
DGND
P
Digital Power Ground.
