March 2007 ADC08D1500
High Performance, Low Power, Dual 8-Bit, 1.5 GSPS A/D Converter
General Description
The AD C08D1500 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sample rates up to 1.7 GSPS. Consuming a typical 1.8 Watts at 1.5 GSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and in-terpolating architecture, the fully differential comparator de-sign, the innovative design of the internal sample-and-hold amplifier and the lf-calibration scheme enable a very flat respon of all dynamic parameters beyond Nyquist, produc-ing a high 7.25 ENOB with a 748 MHz input signal and a 1.5 GHz sample rate while providing a 10-18 B.E.R. Output for-matting is offt binary and the LVD S digital outputs are compliant with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V. Each converter has a 1:2 demultiplexer that feeds two LVDS bus and reduces the output data rate on each bus to half the sample rate. The two converters can be interleaved and ud as a single 3 GSPS ADC.
The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced expod pad LQFP and operates over the Indus-trial (-40°C ≤ T A≤ +85°C) temperature range.Features
■Internal Sample-and-Hold
■Single +1.9V ±0.1V Operation
■Choice of SDR or DDR output clocking
■Interleave Mode for 2x Sample Rate
暴笑■Multiple ADC Synchronization Capability
■Guaranteed No Missing Codes
■Serial Interface for Extended Control
■Fine Adjustment of Input Full-Scale Range and Offt
■Duty Cycle Corrected Sample Clock
Key Specifications
■Resolution8 Bits ■Max Conversion Rate 1.5 GSPS (min)■Bit Error Rate10-18 (typ)■ENOB @ 748 MHz Input7.25 Bits (typ)■DNL±0.15 LSB (typ)■Power Consumption
■—Operating 1.8 W (typ)—Power Down Mode 3.5 mW (typ) Applications
■Direct RF Down Conversion
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■Digital Oscilloscopes
■Satellite Set-top boxes
■Communications Systems
■Test Instrumentation
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Block Diagram
20152153
© 2007 National Semiconductor ADC08D1500 High Performance, Low Power, Dual 8-Bit, 1.5 GSPS A/D Converter
Ordering Information
Industrial Temperature Range
(-40°C < T A < +85°C)
NS Package
ADC08D1500CIYB 128-Pin Expod Pad LQFP
ADC08D1500EVAL
Evaluation Board
Pin Configuration
20152101
* Expod pad on back of package must be soldered to ground plane to ensure rated performance.
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A D C 08D 1500
Pin Descriptions and Equivalent Circuits
Pin Functions
Pin No.Symbol Equivalent Circuit Description
3OutV / SCLK Output Voltage Amplitude and Serial Interface Clock. Tie this pin high for normal differential DCLK and data amplitude. Ground this pin for a reduced differential output amplitude and reduced power consumption. See Section 1.1.6. When the extended control mode is enabled, this pin functions as the SCLK input which clocks in the rial data.See Section 1.2 for details on the extended control mode. See Section 1.3 for description of the rial interface.
4OutEdge / DDR /
SDATA
DCLK Edge Select, Double Data Rate Enable and Serial Data
Input. This input ts the output edge of DCLK+ at which the output
data transitions. (See Section 1.1.5.2). When this pin is floating or
connected to 1/2 the supply voltage, DDR clocking is enabled.
When the extended control mode is enabled, this pin functions as
the SDATA input. See Section 1.2 for details on the extended
control mode. See Section 1.3 for description of the rial
interface.
15DCLK_RST DCLK Ret. A positive pul on this pin is ud to ret and synchronize the DCLK outs of multiple converters. See Section 1.5 for detailed description.
26 29
PD
PDQ
Power Down Pins. A logic high on the PD pin puts the entire device
into the Power Down Mode. A logic high on the PDQ pin puts only
the "Q" ADC into the Power Down mode.
30CAL Calibration Cycle Initiate. A minimum 80 input clock cycles logic low followed by a minimum of 80 input clock cycles high on this pin initiates the lf calibration quence. See Section 2.4.2 for an overview of lf-calibration and Section 2.4.2.2 for a description of on-command calibration.
14FSR/ECE Full Scale Range Select and Extended Control Enable. In non-extended control mode, a logic low on this pin ts the full-scale differential input range to 650 mV直觉歌曲
P-P
. A logic high on this pin ts
the full-scale differential input range to 870 mV
P-P
. See Section 1.1.4. To enable the extended control mode, whereby the rial interface and control registers are employed, allow this pin to float
or connect it to a voltage equal to V
A
/2. See Section 1.2 for information on the extended control mode.
127CalDly / DES /
SCS
Calibration Delay, Dual Edge Sampling and Serial Interface Chip
Select. With a logic high or low on pin 14, this pin functions as
Calibration Delay and ts the number of input clock cycles after
power up before calibration begins (See Section 1.1.1). With pin
14 floating, this pin acts as the enable pin for the rial interface
input and the CalDly value becomes "0" (short delay with no
provision for a long power-up calibration delay). When this pin is
floating or connected to a voltage equal to V
A
/2, DES (Dual Edge
Sampling) mode is lected where the "I" input is sampled at twice
the input clock rate and the "Q" input is ignored. See Section
1.1.5.1.
ADC08D1500
Pin Functions Pin No.
Symbol
Equivalent Circuit
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Description
1819CLK+CLK-
LVDS Clock input pins for the ADC. The differential clock signal must coupled to the pins. The input signal is sampled on the falling edge of CLK+. See Section 1.1.2 for a description of acquiring the input and Section 2.3 for an overview of the clock inputs.
1110.2223
V IN I+V IN I−.V IN Q+V IN Q−
Analog signal inputs to the ADC. The differential full-scale input range is 650 mV P-P when the FSR pin is low, or 870 mV P-P when the FSR pin is high.
7
V CMO
Common Mode Voltage. The voltage output at this pin is required to be the common mode input voltage at V IN + and V IN − upling is ud. This pin should be grounded coupling is ud at the analog inputs. This pin is capable of sourcing or sinking 100μA. See Section 2.2.
31V BG Bandgap output voltage capable of 100 μA source/sink.126
CalRun
Calibration Running indication. This pin is at a logic high when calibration is running.
32
R EXT
External bias resistor connection. Nominal value is 3.3k-Ohms (±0.1%) to ground. See Section 1.1.1.
3435Tdiode_P Tdiode_N Temperature Diode Positive (Anode) and Negative (Cathode) for die temperature measurements. See Section 2.6.2.
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A D C 08D 1500
Pin Functions
Pin No.Symbol Equivalent Circuit Description
83 / 78
84 / 77
85 / 76
86 / 75
89 / 72
90 / 71
91 / 70
92 / 69
93 / 68
94 / 67
95 / 66
96 / 65 100 / 61 101 / 60 102 / 59 103 / 58DI7− / DQ7−
DI7+ / DQ7+
怎样做宫保鸡丁DI6− / DQ6−
DI6+ / DQ6+
DI5− / DQ5−
DI5+ / DQ5+
DI4− / DQ4−
DI4+ / DQ4+
DI3− / DQ3−
DI3+ / DQ3+
DI2− / DQ2−
DI2+ / DQ2+
DI1− / DQ1−
DI1+ / DQ1+
DI0− / DQ0−
DI0+ / DQ0+
I and Q channel LVDS Data Outputs that are not delayed in the
output demultiplexer. Compared with the DId and DQd outputs,
the outputs reprent the later time samples. The outputs
should always be terminated with a 100Ω differential resistor.
104 / 57 105 / 56 106 / 55 107 / 54 111 / 50 112 / 49 113 / 48 114 / 47 115 / 46 116 / 45 117 / 44 118 / 43 122 / 39 123 / 38 124 / 37 125 / 36DId7− / DQd7−
DId7+ / DQd7+
DId6− / DQd6−
DId6+ / DQd6+
DId5− / DQd5−
DId5+ / DQd5+
DId4− / DQd4−
DId4+ / DQd4+
DId3− / DQd3−
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DId3+ / DQd3+
DId2− / DQd2−
数列求和方法DId2+ / DQd2+
DId1− / DQd1−
DId1+ / DQd1+
DId0− / DQd0−
DId0+ / DQd0+
I and Q channel LVDS Data Outputs that are delayed by one CLK
cycle in the output demultiplexer. Compared with the DI/DQ
outputs, the outputs reprent the earlier time sample. The
outputs should always be terminated with a 100Ω differential
resistor.
79 80OR+
OR-
Out Of Range output. A differential high at the pins indicates that
the differential input is out of range (outside the range ±325 mV or
±435 mV as defined by the FSR pin).
82 81DCLK+
DCLK-
Differential Clock outputs ud to latch the output data. Delayed
and non-delayed data outputs are supplied synchronous to this
signal. This signal is at 1/2 the input clock rate in SDR mode and
at 1/4 the input clock rate in the DDR mode. The DCLK outputs
are not active during a calibration cycle, therefore this is not
recommended as a system clock.
2, 5, 8, 13,
16, 17, 20, 25, 28, 33,
128V
A
Analog power supply pins. Bypass the pins to ground.
40, 51 ,62,
73, 88, 99, 110, 121V
DR
Output Driver power supply pins. Bypass the pins to DR GND.
1, 6, 9, 12,
21, 24, 27,
41
GND Ground return for V A.
ADC08D1500
Pin Functions Pin No.Symbol Equivalent Circuit
Description
42, 53, 64,74, 87, 97,108, 119DR GND
Ground return for V DR .
52, 63, 98,109, 120
NC
No Connection. Make no connection to the pins.
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A D C 08D 1500
