SSM222b
Digital MEMS Microphone with bottom sound opening
Rev. 0.3 — December 2008 Preliminary Product Data Sheet 1. Product Profile
The SSM222b is a silicon microphone with digital output and consists of a nsor bad on MEMS technology (M icro-E lectro-M echanical-S ystem) and an ASIC included in one package. The internal ASIC is ud for pre-amplification of the MEMS nsor output signals to achieve high nsitivity and to perform the Analog-to-Digital Conversion bad on the ΔΣ over-sampling principle. A flat frequency respon up to 20kHz and high Signal-to-Noi Ratio offer a unique acoustic performance. The microphone with its bottom sound opening offers a flexible design and is packaged for surface mounting and high-temperature re-flow asmbly.
1.1 Features
• 4.0 mm x 3.0 mm x 1.0 mm surface mount package
• Bottom sound opening offers flexible design
• Flat frequency respon up to 20kHz
• High SNR
• Accurate ADC bad on ΔΣ over-sampling principle
• Serial Digital Output (PDM)
• Left/Right channel lection for multiple microphone application
• Reflow solderable and SMD compatible
• Power Down (Sleep) Mode: data output is in high impedance state
• Compression of high sound pressure levels for better acoustic performance
1.2 Applications
The SSM222b is designed for
• Mobile Handts秦杜虎符
• Digital Still Cameras
• Camcorders
• Headts
• Audio Players
ESD Caution
ESD (Electrostatic discharge) nsitive device. This product features proprietary protection circuit.
However, damage may occur on devices subjected to high energy ESD. Therefore care should be
taken during transport and handling to avoid performance degradation or loss functionality.
2. Characteristics
Test Conditions for the electro acoustic parameters are +25°C and 60% - 70 % R.H, unless otherwis
e noted. The polarity of the output is non-inverting, which means that an increasing pressure on the membrane results in a increasing output voltage (positive). Plea refer also to NXP’s Application Note for MEMS microphones. The specification is met with 2.4MHz clock frequency and supply voltage V DD =1.8V.
二维码营销
Parameter Symbol Min Typ Max Unit Comments Directivity Omni-directional
Supply Voltage V DD 1.64
1.8
2.86
V
Nominal Sensitivity (e 2.1) S -26 dBFS f=1kHz, p in=1Pa
Short Circuit Current 1 10 mA Instead of electrical impedance
Current Consumption I supply850
μA V DD = 1.8V
Current Consumption in sleep mode**I sleep50
μA V DD = 1.8V f clk <= f sleep
Signal to Noi Ratio SNR 60.5 dB(A) A-weighted
at
1kHz,1Pa
Power Supply Rejection PSR -70 dBFS
217Hz, 100mVpp, square wave on V DD最小房车
Sensitivity Loss across Voltage dBV/Pa Change in Sensitivity
over 3.6V to 1.5V Frequency Range 100 20000
Hz
电脑不能打字1 %
1kHz,
100dBSPL
2 %
1kHz,
110dBSPL Total Harmonic Distortion THD+N
5 %
1kHz,
115dBSPL 2.1 Nominal Sensitivity
The nominal nsitivity of the microphone is defined at 94dBSPL and 997Hz after the phone PCB asmbly process, which consists of two reflow rounds (top and bottom side reflow).
九儿吉他谱
The microphone will fall into sleep mode when the external clock frequency is below 1MHz (e also 2.4 Digital Interface Conditions).
dBFS is defined as the amplitude expresd as a level in decibels relative to full-scale amplitude (20 times the common logarithm of the amplitude over the full-scale amplitude).
The Full Scale Amplitude is defined as the amplitude of a 997 Hz sine wave signal who positive peak value reaches the positive digital full scale, leaving the negative maximum code unud. Due to the fact that Full Scale Amplitude is bad on a sine wave, it will be possible with square-wave test signals to read as much as +3,01 dBFS.
Sensivity Change vs. Temperature
2.2 Distortion
Measurement of the Distortion is done according to tup in 2.6.
2.3 SNR Measurement
Measurement of the Signal to Noi Ratio is done according to 2.6.毛蟹炒年糕
The SNR measurement is taken as the ratio in dBFS scale between Nominal Sensitivity (at 94dBSPL and
997Hz in an anechoic chamber) and the A-weighted idle noi floor (measured in a silent anechoic chamber) of the microphone.
2.4 Digital Interface Conditions
The data output is a PDM (Pul-density modulation) signal, which has to be decimated (low-pass filtered) in the audio codec or digital baband in the application. The ΔΣ modulator is of 4th order.
When the microphone is not powered, clock input and data output of the microphone are in high impedance state.
怎么做壁纸
Channel Data Configuration & Interface Timing Chart
A stereo operation of the microphone is accomplished by connecting the Left/Right Channel Selection (L/R) pin either to V dd or GND in the application PWB. Depending on the level of L/R signal, the DATA signal is valid either during high or low time of the CLK signal. To ensure a non-overlapping pha of DATA valid between two different microphones, t delay is always longer than t hold (same supply voltage and ambient temperature, e timing chart below whereas t delay is
B and t hold is A)
Data symbol Min. Typ. Max. Unit
t delay110 ns
t hold 2 ns
The clock signal of the microphone is of high impedance type. Data signal output is a three state output from the microphone.
Right channel:
When a falling CLK is detected, the Data is actively driven. When a rising CLK is detected, the Data is high-Z. Left channel:
When a falling CLK is detected, the Data is high -Z. When a rising CLK is detected, the Data is actively driven.
Data symbol Data asrted at Data sampled at L/R connected to
Right Falling CLK edge Rising CLK edge GND
Left Rising CLK edge Falling CLK edge VDD
Interface Parameters
Parameter Min. Typ. Max. Unit
Operating Clock Frequency 1 3.25 MHz
Performance Clock frequency 2.4 MHz
Duty 40 60
% V DD 1.64 2.86
V Low Level Input Voltage V IL 0 0.3*V DD V
V DD V DD V High Level Input Voltage V IH 0.7*
Low Level Output Voltage V OL GND GND + 0.4 V
Parameter Min. Typ. Max. Unit
High Level Output Voltage V OH V DD – 0.5 V DD V DD
ns Ri Time t ri 1.6
ns Fall Time t fall 1.6
The microphone will fall into sleep mode when the external clock frequency is below 1MHz.
Sleep Mode Detection
If the clock frequency on the CLK pad goes below f sleep (1MHz), the microphone enters into sleep mode to minimize power consumption. Once the clock returns to a value above f sleep, the device exits sleep mode and enters in normal operation mode.
In sleep mode the data output is in high impedance state (tristate mode), if the external clock signal stays oscillating it can remain ether on logic 0 or logic 1.
Parameter Symbol Min. Typ. Max. Unit
怎么样会发烧Wake-up time twakeup10 ms
Fall-asleep time t asleep10 ms Clock frequency threshold for sleep mode f sleep 1 950 kHz
