Verilog编写7人投票选择器
Verilog编写7人投票选择器
module vote7(pass,vote,abnt,agree,object,outabnt); outputpass,agree,object,outabnt;
input[6:0] vote,abnt;
reg[2:0] object,agree,outabnt;
integeri;
reg pass;
always@(abnt or vote)
begin
object=0;
agree=0;
outabnt=7;
for(i=0;i<=6;i=i+1)
begin
if(abnt[i])
begin
outabnt=outabnt-1;
if(vote[i]) agree=agree+1;
el object=object+1;
end
end
if(agree[2:0]>=object[2:0]) pass=1;
el pass=0;
end
endmodule
