Chapter 1:Ove如何制作图表
rview for the Stratix IV Device Family Feature Summary
Stratix IV Device Handbook
Volume 1
Stratix IV GT Devices
Stratix IV GT devices provide up to 48 CDR-bad transceiver channels per device:
■Thirty-two out of the 48 transceiver channels have dedicated PCS and PMA
circuitry and supvc作用
port data rates between 600 Mbps and 11.3Gbps
■
The remaining 16 transceiver channels have dedicated PMA-only circuitry and
support data rates between 600 Mbps and 6.5Gbps 1The actual number of transceiver channels per device varies with device lection. For
more information about the exact transceiver count in each device, refer to Table 1–7 on page 1–16.
1For more information about Stratix IV GT devices and transceiver architecture, refer to the Transceiver Architecture in Stratix IV Devices chapter.
Figure 1–3 shows a high-level Stratix IV GT chip view.
Figure 1–3.Stratix IV GT Chip View (1)
Note to Figure 1–3:
(1)Resource counts vary with device lection, package lection, or both.
Chapter 1:Overview for the Stratix IV Device Family Architecture Features
Stratix IV Device Handbook
Vo洛东江战役
lume 1
Architecture Features
The Stratix IV device family features are divided into high-speed transceiver features and FPGA fabric and I/O features.
1The high-speed transceiver features apply only to Stratix IV GX and Stratix 更强壮的英文
IV GT
devices.
High-Speed Transceiver Features
The following ctions describe high-speed transceiver features for Stratix IV GX and GT devices.
Highest Aggregate Data Bandwidth
Up to 48 full-duplex transceiver channels supporting data rates up to 8.5Gbps in Stratix IV GX devices and up to 11.3Gbps in Stratix IV GT devices.
Wide Range of Protocol Support
Physical layer support for the following rial protocols:
■Stratix IV GX—PCIe Gen1 and Gen2, GbE, Serial RapidIO, SONET/SDH,
XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre Channel, SFI-5, GPON,
SAS/SATA, HyperTransport 1.0 and 3.0, and Interlaken
■Stratix IV GT—40G/100G Ethernet, SFI-S, Interlaken, SFI-5.1, Serial RapidIO,
SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, 3G-SDI, and Fibre Channel
■Extremely flexible and easy-to-configure transceiver data path to implement
proprietary protocols
■PCIe Support
■Complete PCIe Gen1 and Gen2 proto养胃水果
col stack solution compliant to P女性魅力
CI
Express ba specification 2.0 that includes PHY-MAC, Data Link, and
transaction layer circuitry embedded in PCI Express hard IP blocks
f For more information, refer to the PCI Express Compiler Ur Guide .
■
Root complex and end-point applications ■
x1, x4, and x8 lane configurations ■
PIPE 2.0-compliant interface ■
Embedded circuitry to switch between Gen1 and Gen2 data rates ■Built-in circuitry for electrical idle generation and detection, receiver detect,
power state transitions, lane reversal, and polarity inversion
■8B/10B encoder and decoder, receiver synchronization state machine, and
300 parts per million (ppm) clock compensation circuitry
■
Transaction layer support for up to三本是什么意思
two virtual channels (VCs)
