MEMORY存储芯片TMS320F28032PNT中文规格书

TMS320C6745,TMS32吐血是什么原因 0C6747

SPRS377F–SEPTEMBER2008–REVISEDJUNE2014

6.8.2GPIOPeripheralInput/OutputElectricalData/Timing

Table6-9.TimingRequirementsforGPIOInputs(eFigure6-10)

(1)

No.PARA维e直接涂脸有什么效果 METERMINMAXUNIT

1tPulduration,GPn[m]asinputhigh2Cns

2tPulduration,GPn[m]asinputlow2Cns

(1)ThepulwidthgivenissufficienttogenerateaCPUinterruptoranEDMAevent.However,ifaurwantstohaveC6745/6747

(2)C=SYSCLK4periodinns.

w(GPIH)

w(GPIL)

(1)(2)

(1)(2)

recognizetheGPIxchangesthroughsoftwarepollingoftheGPIOregister,theGPIxdurationmustbeextendedtoallowC6745/6747

enoughtimetoaccesstheGPIOregisterthroughtheinternalbus.

Table6-10.SwitchingCharacteristicsOverRecommendedOperatingConditionsforGPIOOutputs

(国际巨星排行榜 eFigure6-10)

No.PARAMETERMINMAXUNIT

3tPulduration,党委工作总结 GPn[m]asoutputhigh2Cns

4tPulduration,GPn[m]asoutputlow2Cns

(1)Thisparametervalueshouldnotbeu彩笔用英语怎么说 dasamaximumperformancespecification.Actualperformanceofback-to-backaccessofthe

(2)C=SYSCLK4periodinns.

w(GPOH)

w(GPOL)

(1)(2)

(1)(2)

GPIOisdependentuponint不辍 ernalbusactivity.

2

1

GPn[m]asinput

3

GPn[m]asoutput

4

Figure6-10.GPIOPortTiming

6.8.3GPIOPeripheralExternalInterruptsElectricalData/Timing

Table6-11.TimingRequirementsforExternalInterrupts(eFigure6-11)

(1)

No.PARAMETERMINMAXUNIT

1tWidthoftheexternalinterruptpullow2Cns

2tWidthoftheexternalinterruptpulhigh2Cns

(1)ThepulwidthgivenissufficienttogenerateaninterruptoranEDMAevent.However,ifaurwantstohaveC6745/6747recognize

(2)C=SYSCLK4periodinns.

w(ILOW)

w(IHIGH)

(1)(2)

(1)(2)

theGPIOchangesthroughsoftwarepollingoftheGPIOregister,theGPIOdurationmustbeextendedtoallowC6745/6747enough

timetoaccesstheGPIOregisterthroughtheinternalbus.

2

1

GPn[m]asinput

Figure6-11.GPIOExternalInterruptTiming

Copyright2008–2014,TexasInstrumentsIncorporated

PeripheralInformationandElectricalSpecifications81

SubmitDocumentationFeedback

ProductFolderLinks:TMS320C6745TMS320C6747

TMS320C6745,TMS320C6747

SPRS377F–SEPTEMBER2008–REVISEDJUNE2014

6.9EDMA

Table6-12isthelistofEDMA3ChannelContollerRegistersandTable6-13isthelistofEDMA3Transfer

Controllerregisters.

Table6-12.EDMA3ChannelController(EDMA3CC)Registers

BYTEADDRESSACRONYMREGISTERDESCRIPTION

0x01C00000PIDPeripheralIdentificationRegister

0x01C00004CCCFGEDMA3CCConfigurationRegister

0x01C00200QCHMAP0QDMAChannel0MappingRegister

0x01C00204QCHMAP1QDMAChannel1MappingRegister

0x01C00208QCHMAP2QDMAChan以欣赏为话题的作文 nel2MappingRegister

0x01C0020CQCHMAP3QDMAChannel3MappingRegister

0x01C00210QCHMAP4QDMAChannel4MappingRegister

0x01C00214QCHMAP5QDMAChannel5MappingRegister

0x01C00218QCHMAP6QDMAChannel6MappingRegister

0x01C0021CQCHMAP7QDMAChannel7MappingRegister

0x01C00240DMAQNUM0DMAChannelQueueNumberRegdanger是什么意思 ister0

0x01C00244DMAQNUM1DMAChannelQueueNumberRegister1

0x01C00248DMAQNUM2DMAChannelQueueNumberRegister2

0x01C0024CDMAQNUM3DMAChannelQueueNumberRegister3

0x01C00260QDMAQNUMQDMAChannelQueueNumberRegister

0x01C00284QUEPRIQueuePriorityRegister

0x01C00300EMREventMisdRegister

0x01C00308EMCREventMisdClearRegister

0x01C00310QEMRQDMAEventMisdRegister

0x01C00314QEMCRQDMAEventMisdClearRegister

0x01C00318CCERREDMA3CCErrorRegister

0x01C0031CCCERRCLREDMA3CCErrorClearRegister

0x01C00320EEVALErrorEvaluateRegister

0x01C00340DRAE0DMARegionAccessEnableRegisterforRegion0

0x01C00348DRAE1DMARegionAccessEnableRegisterforRegion1

0x01C00350DRAE2DMARegionAccessEnableRegisterforRegion2

0x01C00358DRAE3DMARegionAccessEnableRegisterforRegion3

0x01C00380QRAE0QDMARegionAccessEnableRegisterforRegion0

0x01C00384QRAE1QDMARegionAccessEnableRegisterforRegion1

0x01C00388QRAE2QDMARegionAccessEnableRegisterforRegion2

0x01C0038CQRAE3QDMARegionAccessEnableRegisterforRegion3

Q0E0-Q0E15EventQueueEntryRegistersQ0E0-Q0E150x01C00400-0x01C0043C

Q1E0-Q1E15EventQueueEntryRegistersQ1E0-Q1E150x01C00440-0x01C0047C

QSTAT0Queue0StatusRegister0x01C00600

QSTAT1Queue1StatusRegister0x01C00604

QWMTHRAQueueWatermarkThresholdARe高仁尼 gister0x01C00620

CCSTATEDMA3CCStatusRegister0x01C00640

ER0x01C01000EventRegister

ECR0x01C01008EventClearRegister

GLOBALREGISTERS

(1)

GLOBALCHANNELREGISTERS

(1)Onpreviousarchitectures,theEDMA3TCprioritywascontrolledbythequeuepriorityregister(QUEPRI)intheEDMA3CCmemory-

map.Howeverforthisdevice,theprioritycontrolforthetransfercontrollersiscontrolledbythechip-levelregistersintheSystem

ConfigurationModule.Youshoulduthechip-levelregistersandnotQUEPRItoconfiguretheTCpriority.

PeripheralInformationandElectricalSpecifications82

Copyright2008–2014,TexasInstrumentsIncorporated

SubmitDocumentationFeedback

ProductFolderLinks:TMS320C6745TMS32芬兰签证 0C6747