用选择信号赋值语句（with-lect）和移位操作符来实现38译码器

⽤选择信号赋值语句（with-lect）和移位操作符来实现38译码

VHDL实现如下:

LIBRARY IEEE;

USE IEEE.STD_LOGIC_;

ENTIDY Trans38 IS

PORT(

A:IN STD_LOGIC_VECTOR(2 DOWNTO 0);

Y:OUT STD蚯蚓 _LOGIC_VECTOR(7 DOWNTO 0)

)标题分级 ;

END Trans38;

ARCHITECTURE behav OF trans38 IS

BEGIN

WITH A SELECT

Y<= "00000000" SLL CONV_INTEGER(A) when "0001",

美国女明星 "00000000" SLL CONV_INTEGER(A) when "001" , --有效输出为⾼电平

"00000000" SLL CONV_INTEGER(A) when "010" ,

"00000000" SLL CONV_INTEGER(A) when "011" ,

"00000000" SLL CONV_INTEGER(A) when "100" ,

"00000000" SLL CONV_INTEGER(A) when "1海峡两岸关系 01" ,

"00000000" SLL CONV_INTEGER(A) wh疝气治疗 看见柴静 en "110" ,

"00000000" SLL CONV_INTEGER(A) when "111" ;

END behav;

注：来⾃互联⽹，未经实机测试，谨慎使⽤；

器