FPGA可编程逻辑器件芯片5SGXFC5C6F23I7N中文规格书

CycloneII Memory Blocks

ca writing is controlled only by the write enable signals. There is no

clear port to the byte enable register洞天是什么意思 s. M4K blocks support byte enables

when the write port has a data width of 1, 2, 4, 8, 9, 16, 18, 32, or 36 bits.

When using data widths of 1, 2, 4, 8, and 9 bits, the byte enable behaves

as a redundant write enable becau the data width is less than or equal

to a single byte. Table8–3 summarizes the byte lection.

Table8–3.Byte Enable for CycloneII M4K BlocksNote(1)

Affected Bytes

byteena[3..0]

[0]= 1[0][1..0][3..0][7..0][8..0][7..0][8..0][7..0][8..0]

[1]1-----[15..8][17..9][15..8][17..9]

=

[2]1-------[23..16][26..18]

=

[3]1-------[31..24][35..27]

=

Note to Table8–3:

(1)Any combination of byte enables i可以用牛奶吃药吗 s possible.

datain data窗花寓意 in datain datain全日制劳动合同 datain datain datain datain datain

1248916183236

Table8–4 shows the byte enable port control for true dual-port mode.

Table8–4.Byte Enable Port Control for True Dual-Port Mode

byteena [3:0]Affected Port

[1:0]Port A (1)

[3:2]Port B (1)

Note to Table8–4:

(1)For any data width up to 18 for each port.

Figure8–2 shows how the wren and byteena signals control the

operations of the RAM.

When a byte enable bit is de-asrted during a write cycle, the

corresponding data byte output appears as a “don’t care” or unknown

value. When a byte enable bit is asrted during a write cycle, the帮助英语

corresponding data byte output is the newly written data.

Cyclone II Device Handbook, Volume 1

Overview

Figure8–1.M4K Control Signal Selection

Dedicated

Row LAB

Clocks

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

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Local

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Local

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Local

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Local

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Local

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Local

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Local

Interconnect

6

clock_b

clock_aclocken_a

clocken_b

renwe_aaddressstall_a

renwe_baddressstall_b

aclr_a

aclr_b

byteena_b

byteena_a

Parity Bit Support

Error detection using parity check is possible using the parity bit, with

additional logic implement金色花教学设计 ed in LEs to ensure data integrity. Parity-size

data words can also be ud for other purpos such as storing

ur-specified control关于春天的古诗 bits.

f

Refer to the Using Parity to Detect Errors White Paper for more

information.

Byte Enable Support

All M4K memory blocks support byte enables that mask the input data so

that only specific bytes of data are written. The unwritten bytes retain the

previous written value. The write enable (wren) signals, along with the

byte enable (byteena) signals, control the RAM block’s write operations.

The default value for the byte enable signals is high (enabled), in which

Cyclone II Device Handbook, Volume 1