Design and Implementation of High-Efficiency and Low-Power
DC-DC Converter with PWM/PFM Modes
Jing Wang,Wenchao Gong *,Lenian He
Institute of VLSI Design,Zhejiang University,Hangzhou 310027,China
*Email:gongwc@vlsi.zju.edu
Abstract --A high-efficiency low-power multimode DC-DC converter with pul-width modulation (PWM)and pul-frequency modulation (PFM)is propod.This converter works in PWM mode on heavy load condition.In order to improve efficiency,it switches to PFM mode on light load condition.With suitable control and mode switch method,both simulation and chip test results indicate that the converter performs amless switching between PWM and PFM modes.The total output voltage error,including line and load regulation,is less than 2%,the maximum quiescent current is less than 15μA,the maximum of efficiency reaches 92.6%.Simulated and implemented in CSMC 0.5μm CMOS process.1.Introduction
Efficiency is one of the primary considerations in DC-DC converter design.Arbetter,et al [1]indicated that the power loss in DC-DC converter can be classified into three categories:conduction loss,switching loss and fixed loss.Conduction loss is induced by ries resistances of load,thus it is proportional to the square of load current.Switching loss is the the energy consumed on charging /discharging gates and switches,thus it is proportional to switching frequency.Fixed loss is determined by the quiescent current.So the efficiency of DC-DC converter can be expresd as:
2out L
22out L para DD gate F ()I R I R R f V C P =
+++(1)In which I out is load current,R L is load resistor,R para is the sum of transistor on-resistancee
s,inductor winding resistance and capacitor equivalent ries resistance,f is switching frequency,C gate is the equivalent gate capacitance of power transistors,V DD is power supply voltage,and P F indicates fixed loss.
Pul-width modulation (PWM)converters work at a fixed frequency.Their switching loss and fixed loss are independent of load current.If load current is large,conduction loss dominates denominator in equation (1),thus the efficiency is approximately R L /(R L +R para ),which is nearly 1for R L >>R para .On the other hand,switching loss and fixed loss overwhelm conduction loss when load current is low,thus ηdescends significantly.
Considering this fact,pul-frequency modulation
(PFM)mode is utilized [1]-[5].With a lower frequency,PFM mode reduced switching loss to maintain high efficiency.
For wide range of load current variation,PWM and PFM mode show their merits in heavy and light load application respectively.Thus multimode DC-DC converter switches smoothly between them should be taken into account.
Motivated by the concerns above,a high-efficiency,low-power DC-DC converter with PWM and PFM modes is propod in this paper.2.Circuit
Design
Figure 1.Block diagram of DC/DC converter 2.1System Architecture
The overall block diagram of the propod DC-DC converter is shown in Figure 1.The value of output voltage in steady state is determined as follows:
F1out F21500mV
R
V R =+(2)The control block determines the control loops of PWM /PFM modes.
The converter switches between modes in the following way:After power-on,when V in >3V and V out <1.8V ,converter enters soft-start stage.Strictly soft-start is also PWM mode.Difference is,I limit in soft-start stage ris step by step.I limit will be t to 100mA,200mA and then 300mA.Each step takes about 250us.If t >750ns or before that V out >1.8V ,converter enters PWM mode.I limit is t to 480mA in this mode.
PWM and PFM modes are steady states.In PWM mode,if I L is continuous the converter stays in PWM
1-4244-1132-7/07/$25.00 © 2007 IEEE
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mode.If I L≤0,which indicates the I L is discontinuous and thus I out is low,the converter switches to PFM mode in order to improve efficiency.
In PFM mode,when V out reaches its upper limit V out_high=1.84V,the converter enters sleep.During sleep both power transistors and most functional blocks are off. The converter will return to PFM mode operation when V out falls to V out_low=1.82V.If heavy load current drag V out to V out,0=1.80V,the converter will switch back to PWM mode.
During operation,if V in falls to lower than2.8V,the converter will enter power-off state.Then converter will wait until V in>3V, converter re-enters soft-start.
2.2PWM Mode Operation
When V out is lower than 1.8V,or the inductor current is continuous,the converter operates in PWM mode. Figure2 shows the PWM voltage control loop.
Figure2.Control loop of PWM mode
V in is input voltage,V ref is0.5V reference voltage, V comp proportional to the product of V in and duty cycle D, and CLK is an1MHz clock signal. G m converts V the voltage error of V ref and V FB(V out feed-back),into error current i e.V-I(V oltage-to-current)converter generates a current I ref which is proportional to V in.I ref and i e charge up capacitor C1,which is part of the saw-tooth gener
ator.If M1is off,the voltage on C1 ramps up with a slope of (I ref+i e)/C1;If M1is on,C1 discharges instantly to the ground.Since C1is sufficiently small with its value t to2pF,the power loss during charge and discharge of C1contributes little to the total power consumption of the converter.The saw-tooth voltage,which appears at the upper plate of C1, and V comp are the inputs of PWM comparator.The PWM comparator generates PWM signals and controls the on and off of power transistors through D-type flip-flop.
A PWM working cycle starts with the rising edge of CLK.It turns MOSFET SP on and SN off.Inductor current I L ramps up with a slope of(V in-V out)/L.During this period, M1’s gate is shut,so capacitor C1is charged up by current I ref and i e.When the voltage on C1exceeds V comp,PWM comparator’s output falls,turning SP off, SN on.At the moment, M1is turned on,C1is totally discharged,thus PWM comparator’s output turns back to high level immediately.For the rest of the cycle, condition remains unchanged.During this period,I L ramps down with a slope of V out/L,until a new cycle starts at the rising edge of CLK.In this cycle,when I L<I out,V out falls,when I L>I out,V out ris.In stable condition,V out fluctuates in each cycle.
The control strategy of PWM mode is comprid of V out feed-back and V in feed forward.While the feed-back control loop ensures V out stability on I ou t change, feed-forward control benefits line reg说一说
ulation considerably.As shown in Figure2,PWM duty cycle is related with the V out and i e,thus V out error will be corrected.Duty cycle is also directly affected by I ref and V in,thus power supply rejection(PSR)is improved.
2.3PFM Mode Operation
When V out is over1.8V and discontinuous current occurs in the inductor,the converter operates in PFM mode.To reduce the switch loss,PFM mode us 0.5MHz frequency,lower than PWM’s frequency.
Figure3shows the control loop of PFM mode.I peak is the max inductor current,who value is approximately120mA and is proportional with V in.PG and NG are gate voltages of SP and SN,respectively. V high and V low are the upper and lower bonds of V FB.Their values are t to be510mV and505mV in our design. Thus,the upper and lower bounds can be determined as equation (3):
F1
high
F2
F1
out_low low
F2
F1
out out_high out_low high low
F2
out_high
(1)
(1)
(1)()
R
V
R
R
V V
R
R
V V V V V
R
V+
=+
=−=+−
筝柱=
(3)
At the beginning of each PFM cycle,V FB<V low and I L<I peak,SP is on and SN is off.I L ris with a slope of (V in-V out)/L.As I L exceeds I peak,CPC(Current Peak Comparator)outputs low and turns off SP,turns on SN, conquently I L ramps down with a slope of V out/L.Since I L<I peak,CPC outputs high,and V out decreas for I L<I out. As I L falls to zero,ZCC(Zero Current Comparator) outputs high and turns off SN.If V FB<V high at the moment,SP will turn on simultaneously and a new PFM cycle begins;otherwi if V FB>V high,both SP and SN are off and the converter enters sleep.During sleep,most blocks are shut down,load capacitor C discharges and V out decreas.The PFM control will return to work
597
when V FB <V low .
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I
I
Figure
3.
Control loop
of PFM mode
3.Experimental Results
CSMC 0.5um CMOS process and
Cadence Spectre
simulator
is
ud in交换机有什么用
清炖鱼怎么做simulation.Simulations temperatures are all t to 27
立方米怎么打
(a)Startup
(b)Load regulation
detail
Figure 4. Simulated startup and 3mA~200mA load
regulation respon
Figure
4(a)shows
the
startup process.
Soft-start lasts
from 10us to
750us. Since
I limit
goes up step
by
少年包青天歌曲step,V
out increas
gradually and startup overshoot
is
below
30mV .
Figure
4(b)is
the
detailed
load regulation signal.Load current switch from 200mA to 3mA and then switch back.When the converter outputs a low current,converter works in PFM mode.Converter switch V out is approximately 100mV .And the waveform shows good stability during load transition.During steady operation,
the offt of V out is less than 60mV
.
Figure 5. 3.6V~4.6V line regulation transient signal Figure 5shows the simulation waveforms for V in
stepping between 3.6V and 4.6V .I out =150mA and V out =1.8V .When V in jumps within 1μs,th
e maximum overshoot of V out is less than 40mV .The system shows good stability during V in transition.
89.00%
89.50%90.00%90.50%
91.00%91.50%
92.00%
92.50%
93.00%0
50
100绿豆芽做法
150
200
250
Figure 6. Efficiency versus I out simulation curves Figure 6shows the steady-state efficiency η’s curves.The curves cover different V in and I out ,show that the efficiency ηis around 90%and its peak value is 92.6%.To compare with,the PWM DC/DC converter in Ref.[6]us 0.5μm standard CMOS process has an optimal efficiency of 76.8%;the current-mode PWM DC/DC buck converter in Ref.[7]us 0.6μm CMOS process has 89.5%peak efficiency
Figure 7.Test chip layout overview
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Test chip of the propod DC/DC converter (Figure 7)is implemented by CSMC 0.5um CMOS mixed-signal process.The chip’s total area is 1.3mm×1.52mm .Multiple pads are adopted as trimming pads of reference
voltage.
Figure 8. Load regulation experimental result Figure 8shows the experimental waveforms of V out
and I out for step changes in I out .V in is t to 4V .When I out steps between 3mA and 180mA peri
odically,the converter achieves a stable V out and a peak-to-peak fluctuation of less than 100mV .Nois of V out in Figure 8can be reduced by adopting off-chip low-pass filter with high
Q.
Figure 9 Line regulation experimental result Figure 9shows the experimental waveforms of V in
and V out for step changes in V in .I out is t to 180mA and the temperature is 20 .When V in steps between 3V and 4V periodically,V out remains stable around 1.8V .4.Summary
A high-efficiency low-power multimode DC-DC converter with PWM /PFM is propod in this paper.If inductor current is continuous,converter keeps working in PWM mode at 1MHz.When inductor current is discontinuous,converter enters in PFM mode.In this mode,frequency is reduced to less than 0.5MHz,ensuring high efficiency within a large range (0~250mA)of load current variation.In PFM mode,as the output voltage reaches approximately 102%of the anticipated output value of 1.8V ,the converter enters sleep,during which power supplies of most functional circuits are cut off,thus the quiescent current decreas.When output voltage below 101%of predefined output value,PFM starts again.And if output voltage is even lower than predefined value,converter switch back to PWM mode.In this way,converter switch amlessly between modes,
the output voltage error keeps below ±2%.
Startup is controlled by soft-start block.When power on,soft-start gradually ri the output current limit, ensuring the startup overshoot below 30mV .
The maximum quiescent current is less than 15uA,the maximum of efficiency up to 92.6%.The converter operates smoothly within a temperature range of -40 ~85 .
References
[1]B.Arbetter,R.Erickson,D.Maksimovic,DC-DC converter design for battery-operated systems,in:IEEE 26th Power Electronics Specialists Conference,Atlanta,18-22June 1995, vol.1,pp.103-109.
[2]B.Sahu,G.A.Rincon-Mora,A accurate,low-voltage,CMOS switching power supply with adaptive on-time pul-frequency modulation (PFM)control,IEEE Trans.Circuits and Systems,54(2)(2007)312-321.
[3] B.Sahu,G .A.Rincon-Mora,A high-efficiency,dual-mode,dynamic,buck-boost power supply IC for portable applications,in:18th International Conference on VLSI Design,Kolkata,3-7January 2005, pp. 858-861.
[4]G.-W.Wei,O.Trescas,W.-T.Ng,A dynamic voltage scaling controller for maximum energy saving across full range of load conditions,in:IEEE Conference on Electron Devices and Solid-State Circuits,Hong Kong,19-21December 2005,pp.371-374.
[5]B.Reed,K.Ovens,J.Chen,V .Mayega,S.Issa,A high efficiency ultra-deep sub-micron DC-DC converter for microprocessor applications,in:16th International Symposium on Power Semiconductor Devices and ICs,Kitakyushu,24-27May 2004,pp.59-62.
[6]L.Geng,Q.-H.Li,Z.-B.Shao,A new design strategy for the monolithic buck converters,in: 4th International Power Electronics and Motion Control Conference,Xi'an,14-16August 2004,vol.1,pp.192-196.
[7]C.-F.Lee,P.K.T.Mok,A monolithic current-mode CMOS DC-DC converter with on-chip current-nsing technique,IEEE Journal of Solid-State Circuits,39(1)(2004)3-14.
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