PICMG Specification
Engineering Change Notice 2.0-3.0-002
Topic: Self-Describing Slot Geography
Affected Specification: PICMG 2.0 R3.0
Sponsor(s): Software Interoperability Subcommittee
Participants in Final Ballot Group:
Aculab, Artela Systems, Asis, Force Computers, Hybricon, Intel, LynuxWorks, Matrox, MontaVista Software, National Instruments, Pentair Electronic Packaging, Pigeon Point Systems, PLX Technology, Rittal/Kaparel, SANMINA, Spectel, Sun Microsystems, Wind River Systems
室内设计师之路Description
The focus of this ECN is to enable hardware-independent software to map between: o the geographic address (or physical slot numbers) that are defined for each CompactPCI slot and
o the logical PCI address (bad on the bus, device and function numbers) by which operating systems and device drivers access the boards in tho slots. The emphasis is on systems containing CompactPCI bus on the backplane. Switch fabric-bad architectures, such as tho established by PICMG 2.16 and PICMG 2.17 need to address the issues parately for boards that don’t interface to the CompactPCI bus on the backplane. Both architectures provide for systems with and without CompactPCI bus on the backplane.
Justification
Achieving the above mapping is crucial to achieving two higher level goals: o Enabling application an
d system software to communicate with an operator about specific boards in the system by designating them in a simple and preci manner that is consistent across systems and vendors. The conquences of operator
action on the wrong slot can be vere.
CompactPCI physical slot numbers start at 1 at the top left-most slot and increa quentially. CompactPCI backplanes already provide a binary encoded physical slot number to each slot. Logical PCI address are the likeliest alternative board designators, but can be confusing and error prone for operators.
PCI bus numbers can be different over time in the same system, depending on
board population. Bus numbers in the system are directly affected by the
prence of boards that interface to the CompactPCI bus through transparent PCI-
to-PCI bridges. PCI bus and device numbers are not intuitive. Two systems can
look very similar and have quite different bus number structures. Device numbers of CompactPCI boards are typically in the range 9 to 15, but the ordering of
device numbers within the physical slots of a given gment can be arbitrary.
o For systems bad on PICMG 2.9, the CompactPCI System Management specification, enabling integration of information from two critical domains. The system management domain is bad on the Intelligent Platform Management
Interface (IPMI) and inherently us physical slot numbers to identify boards.
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Meanwhile, the operating system domain typically us PCI logical address to
refer to boards on a CompactPCI bus. PICMG 2.9R1.0 does not provide a
mechanism for hardware-independent software to correlate information between
the domains, each of which may contain unique information critical to the
overall management of a system.
In summary: the overall situation regarding geographic addressing in CompactPCI systems is that backplanes supply a binary encoded geographic address (GA) to each slot, but there is:
o No requirement that boards do anything with it, except in PICMG 2.9 systems, where GA is ud in the IPMI subsystem but not generically accessible to the PCI subsystem.
o No hardware-independent means to get the GA of the slot containing a specific board.
Style
Specific propod changes are provided in the next ction, in the style described below.
ECN text describing changes in the affected document us this font.
Text intended for inclusion in the body of the specification us this font.
Section headers for text intended for inclusion in the body of the specification are preceded with the notation:
<Header Level x> y.z Title
where: x indicates the level of header to be ud, and y.z indicates the anticipated number that would be automatically generated by Microsoft Word by the inclusion of this new ction named Title.
Newly inrted Figure and Table items are assigned numbers in a special ries for this ECN. Figures are numbered E02-Fn, with Tables numbered E02-Tn.
Concurrent with development of this ECR02 for PICMG 2.0R3.0, ECR01 was also in progress to add CompactPCI support for PCI-X. Wherever possible, item numbering in this ECN is chon to be compatible with the changes propod in ECR01. The goal is to minimize the challenges of:
• merging the two ECNs (once both are adopted) into the main specification and
• concurrently using the two ECNs for development guidance in the interim before the merge occurs.
Form for Compliance Claims and Requirement References
Consistent with the PICMG Policies and Procedures for Specification Development, the following form for claims of compliance or requirement references from other PICMG specifications is recommended:
“[This product complies with…] or [component x shall meet the requirements of…] PICMG 2.0 R3.0 as amended by ECN 2.0-3.0-002.”
Specific Propod Changes
Section 1.5 Applicable Documents
Add references to PICMG 2.5, 2.6, 2.7, 2.16, 2.17 and the PCI-to-PCI Bridge spec.
• PCI-to-PCI Bridge Architecture Specification. PCI Special Interest Group, 5200 N.E. Elam Young Parkway, Hillsboro OR 97124-6497, Phone: (503) 696-2000
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• PICMG 2.5, CompactPCI Computer Telephony Specification.
• PICMG 2.61, Bridging Beyond Eight Slots: Common Practices.
• PICMG 2.7, CompactPCI Dual System System Slot Specification.
• PICMG 2.16, CompactPCI Packet Switching Backplane Specification.
• PICMG 2.172, CompactPCI StarFabric Specification.
Minor Update to Section 2.1 Form Factor
Edit the 2nd paragraph on page 14 (just below Figure 2) to clarify the requirements on physical slot numbering.
CompactPCI defines slot numbering bad on the concept of physical and logical slots. Physical slot numbers shall start at 1 in the top-left corner of the card cage. All CompactPCI systems should label all physical slots with their physical slot numbers
1 At this writing, PICMG 2.6 is in development.
2 At this writing, PICMG 2.17 is in development.
within the compatibility glyphs. Figure 2 illustrates physical slot numbering within the compatibility glyphs (e.g., 1) on a backplane. Similar slot labeling should be applied on the subrack if necessary to ensure operator visibility. See Section 4.1.9 for further details on slot labeling and compatibility gl
yphs.
New Section 2.6 Self-Describing Slot Geography
Add a new ction introducing the lf-describing slot geography features of CompactPCI, including the new features introduced by this ECN.
查看cpu温度<Header Level 2> 2.6 Self-Describing Slot Geography
The strong modularity of CompactPCI components allows: 1) a wide range of boards to be installed in a given backplane and 2) the same board (say, a system slot board) to be installed in a wide range of backplanes. The combinations can produce very different slot geographies. The slot geography of a gment of CompactPCI slots is the mapping, for each slot, between:
• the physical slot number of the slot, and
• for peripheral slots, the PCI logical device number by which a board in that slot is addresd on the CompactPCI bus.
Accurate information about the slot geography of a system is crucial to ensuring that application and
system software can communicate with an operator about specific boards in the system by designating them with simple and preci physical slot numbers. Physical slot numbers are far preferable to the likely alternative slot designator: the PCI logical address by which a slot is referenced on the CompactPCI bus. PCI logical address are typically easy for operating systems and device drivers, but can be cryptic and confusing to an operator. The conquences of operator action on the wrong slot can be vere.
This specification’s approach to the challenges has three aspects:
1. Embedded information in backplanes that can electrically lf-describe their slot
geographies and a strong recommendation that slot geography data be made
available to software.
Each CompactPCI slot can include dedicated geographic address pins that
electrically identify the physical slot number to a board installed in that slot.
Additional pins in a system slot can describe the PCI geography of the backplane bus gment created by that slot.
2. A particular mechanism that allows CompactPCI boards (such as system slot
boards) to make this geographic information available to software in a hardware
independent way.中国名酒白酒排行榜
Leveraging the Vital Product Data feature defined by Revision 2.2 of the PCI
Local Bus Specification, CompactPCI boards can provide access to this
geographic information for hardware-independent software.
3. A strong recommendation that CompactPCI subracks include operator-visible
physical slot number labeling.
Together, the facilities can enable simple and preci communication with an operator regarding the location of boards in a system.
New Section 3.1.10 Mapping PCI Device Numbers to ADxx Lines on System Slot Boards
Add a constraint on this mapping to facilitate a simple description of slot geography for backplane gments. Although this is a new constraint that is not prent in PICMG 2.1R3.0, esntially all existing system slot boards are very likely to already meet it.
<Header Level 3> 3.1.10 Mapping PCI Device Numbers to ADxx Lines on System Slot Boards
System Slot boards that create a backplane gment implement a specific mapping from PCI device numbers to ADxx lines for Type 0 configuration cycles targeting that gment. For backplane gments that are created by PCI-to-PCI bridges, that mapping is mandated by the PCI-to-PCI Bridge Architecture specification. For other gments that are created by PCI host bridges:紫罗兰监狱
The PCI-to-PCI bridge mapping should be ud.
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Otherwi, the mapping shall be of the form “xx = ADxx Constant plus or minus Device Number” where ADxx Constant is fixed for a particular backplane
gment. For instance, some host bridges u plus and ADxx Constant = 11; for
backplane gments created by such bridges, xx = 11 + Device Number. The
mandated mapping for PCI-to-PCI bridges us plus and ADxx Constant = 16.
For a quential mapping like AD31 = Device 0, AD30 = Device 1, …, ADxxqq头像女生小清新
Constant would be 31 and the operator would be minus.
Update to Section 3.2.7.6 Geographic Addressing (GA[4..0])
Inrt additional text at the end of this ction on page 26 to note the possibility of providing access to GA data via VPD.
Boards that support Vital Product Data may provide access to this geographic addressing data via special keywords defined in Chapter 6, Vital Product Data (VPD) Requirements. For peripheral boards that support a VPD interface in the CompactPCI bus interface
device, the LC keyword may be implemented to provide a hardware-independent means for software to identify the physical slot in which the board is installed.
New Section 3.2.7.8 Segment Type (ST[1..0])
Define a new field in system slots that helps to identify the PCI geography of the backplane gments created by tho system slots.
<Header Level 4> 3.2.7.8 Segment Type (ST[1..0])
The ST[1..0] signals should be implemented in each system slot to help identify the PCI geography o
f peripheral slots created by tho system slots. Boards that u the ST signals shall pull them up with 10.0 Kohm ±10% resistors.
In a backplane system slot implementing the ST[1..0] signals, the Segment Type created by that system slot shall be encoded on the backplane by grounding and leaving unconnected different combinations of pins. Table E02-T1 defines the Segment Types corresponding to each such combination, with names for specifically assigned types. Segment Type Unknown indicates that a system slot does not support Segment Type identification. Subquent subctions define the Segment Types.
Table E02-T1. Segment Types Identified by ST[1..0]
Segment Type
Name ST[1] (J2-D21) ST[0] (J2-E21)
GND
Rerved GND
Nominal Left GND Open
Nominal Right Open GND
Open
Unknown Open
<Header Level 5> 3.2.7.8.1 Definition and U of Nominal Left and Nominal Right Segments
In Nominal backplane gments, quential logical slots (and the associated ADxx mappings defined in Table 7) occupy quentially numbered physical slots moving away from the system slot, either to the right or to the left.
The following properties apply to Nominal Left gments:
• The GA[4..0] field defines the physical slot number of the system slot.
• The clost distinct (not co-located) peripheral slot is immediately to the left of the system slot that creates it and has a physical slot number one smaller.
