● 春节活动图片Keywords:
微型计算机（Microcomputer）
象棋助手PC（Personal Computer）机
单片微型计算机（Single Chip Microcomputer）
中央处理单元（CPU，Central Processing Unit）
输入输出（I/O，Input/Output）
人生看得几清明随机存取存储器（RAM，Random Access Memory）
只读存储器ROM（Read-only Memory）
专用寄存器（Special Function Register）
程序计数器（PC，Program Counter）
茨菇烧肉的做法累加器（ACC，Accumulator）
程序状态字（PSW，Program Status Word）
堆栈指针（SP，Stack Pointer）
时钟电路（Clock circuit）
复位电路（Ret circuit）
电压（Voltage）
地线（Ground）焦耳和千瓦时换算
● Introduction:
The generic 8031 architecture sports a Harvard architecture, which contains two parate bus for both program and data. So, it has two distinctive memory spaces of 64K X 8 size for both program and data. It is bad on an 8 bit central processing unit with an 8 bit Accumulator and another 8 bit B register as main processing blocks. Other portions of the architecture include few 8 bit and 16 bit registers and 8 bit memory locatio
ns. Each 8031 device has some amount of data RAM built in the device for internal processing. This area is ud for stack operations and temporary storage of data. This ba architecture is supported with onchip peripheral functions like I/O ports, timers/counters, versatile rial communication port. So it is clear that this 8031 architecture was designed to cater many real time embedded needs.
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The following list gives the features of the 8031 architecture:
#Optimized 8 bit CPU for control applications.
#Extensive Boolean processing capabilities.
#64K Program Memory address space.
#64K Data Memory address space.
#128 bytes of onchip Data Memory.
#32 Bi-directional and individually addressable I/O lines.
#Two 16 bit timer/counters.
#Full Duplex UART.
#6-source / 5-vector interrupt structure with priority levels.
#Onchip clock oscillator.
Now you may be wondering about the non mentioning of memory space meant for the program storage, the most important part of any embedded controller. Originally this 8031 architecture was introduced with onchip, ‘one time programmable’ version of Program Memory of size 4K X 8. Intel delivered all the microcontrollers (8051) with ur’s program fud inside the device. The memory portion was mapped at the lower end of the Program Memory area. But, after getting devices, customers couldn’t change any thing in their program code, which was already made available inside during device fabrication.
Figure 1 - Block Diagram of the 8031 Core
*Central Processing Unit:
The CPU is the brain of the microcontrollers reading ur’s programs and executing the expected task as per instructions stored there in. Its primary elements are an 8 bit Arit
hmetic Logic Unit (ALU), Accumulator (Acc), few more 8 bit registers, B register, Stack Pointer (SP), Program Status Word (PSW) and 16 bit registers, Program Counter (PC) and Data Pointer Register (DPTR). The ALU (Acc) performs arithmetic and logic functions on 8 bit input variables. Arithmetic operations include basic addition, subtraction, multiplication and division. Logical operations are AND, OR, Exclusive OR as well as rotate, clear, complement and etc. Apart from all the above, ALU is responsible in conditional branching decisions, and provides a temporary place in data transfer operations within the device. B register is mainly ud in multiply and divide operations. During execution, B register either keeps one of the two inputs and then retains a portion of the result. For other instructions, it can be ud as another general purpo register. Program Status Word keeps the current status of the ALU in different bits. Stack Pointer (SP) is an 8 bit register. This pointer keeps track of memory space where the important register information are stored when the program flow gets into executing a subroutine. The stack portion may be placed in any where in the onchip RAM. But normally SP is initialized to 07H after a device ret and grows up from the location 08H. The Stack Poin
ter is automatically incremented or decremented for all PUSH or POP instructions and for all subroutine calls and returns. Program Counter (PC) is the 16 bit register giving address of next instruction to be executed during program execution and it always points to the Program Memory space. Data Pointer (DPTR) is another 16 bit addressing register that can be ud to fetch any 8 bit data from the data memory space. When it is not being ud for this purpo, it can be ud as two eight bit registers.
*Input / Output Ports:
The 8031's I/O port structure is extremely versatile and flexible. The device has 32 I/O pins configured as four eight bit parallel ports (P0, P1, P2 and P3). Each pin can be ud as an input or as an output under the software control. The I/O pins can be accesd directly by memory instructions during program execution to get required flexibility. The port lines can be operated in different modes and all the pins can be made to do many different tasks apart from their regular I/O function executions. Instructions, which access external memory, u port P0 as a multiplexed address/data bus. At the beginning of an e
xternal memory cycle, low order 8 bits of the address bus are output on P0. The same pins transfer data byte at the later stage of the instruction execution. Also, any instruction that access external Program Memory will output the higher order byte on P2 during read cycle. Remaining ports, P1 and P3 are available for standard I/O functions. But all the 8 lines of P3 support special functions: Two external interrupt lines, two counter inputs, rial port’s two data lines and two timing control strobe lines are designed to u P3 port lines. When you don’t u the special functions, you can u corresponding port lines as a standard I/O. Even within a single port, I/O operations may be combined in many ways. Different pins can be configured as input or outputs independent of each other or the same pin can be ud as an input or as output at different times. You can comfortably combine I/O operations and special operations for Port 3 lines.
*Memory Organization:
The 8031 architecture provides both onchip memory as well as off chip memory expansion capabilities. It supports veral distinctive ‘physical’ address spaces, functional
微波炉怎么清洗ly parated at the hardware level by different addressing mechanisms, read and write controls signals or both:
On chip Program Memory
On chip Data Memory
Off chip Program Memory
Off chip Data Memory
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