November 2006 Cover Page
HYS72T64400HFD–[3S/3.7]–A
HYS72T128420HFD–[3S/3.7]–A HYS72T256420HFD–[3S/3.7]–A
240-Pin Fully-Buffered DDR2SDRAM Modules
DDR2 SDRAM
RoHS Compliant Products
Internet Data Sheet
Rev. 1.2
HYS72T[64/128/256]4[00/20]HFD–[3S/3.7]–A Revision History
Revision History: Rev. 1.2, 2006-11-27
All Adapted internet edition
Page19Updated “Current Spec. and Conditions” on Page19
Previous Revision: Rev. 1.1, 2006-09-26
All Converted to qimonda template
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HYS72T[64/128/256]4[00/20]HFD–[3S/3.7]–A
1
Overview
This chapter describes the main characteristics of the 240-Pin Fully-Buffered DDR2SDRAM Modules product family.
1.1
Features
•240-pin Fully-Buffered ECC Dual-In-Line
DDR2 SDRAM Module for PC, Workstation and Server main memory applications.
•Module organisation one rank 64M ×72, one rank 128M ×72, two ranks 128M ×72, two ranks 256M ×72
•JEDEC Standard Double Data Rate 2
Synchronous DRAMs (DDR2 SDRAMs) with 1.8V (±0.1V) power supply.
•Built with 512Mb DDR2 SDRAMs in 60-ball FBGA Chipsize Packages.
•Re-drive and re-sync of all address, command, clock and data signals using AMB (Advanced Memo
ry Buffer).•High-Speed Differential Point-to-Point Link Interface at 1.5V (Jedec standard pending).
•Host Interface and AMB component industry standard compliant.
•Supports SMBus protocol interface for access to the AMB configuration registers.
三下乡心得•Detects errors on the channel and reports them to the host memory controller.
•Automatic DDR2 DRAM Bus Calibration.•Automatic Channel Calibration.
鸡年吉祥
•Full Host Control of the DDR2 DRAMs.•Over-Temperature Detection and Alert.•Hot Add-on and Hot Remove Capability.•MBIST and IBIST Test Functions.
•Transparent Mode for DRAM Test Support.•Low profile: 133.35mm × 30.35mm
•240 Pin gold plated card connector with 1.00mm contact centers (JEDEC standard pending).
•Bad on JEDEC standard reference card designs (Jedec standard pending).
•SPD (Serial Prence Detect) with 256 Byte rial E 2PROM.Performance:•RoHS Compliant Products 1)
TABLE 1
Performance for DDR2–667 and DDR2–533
1)RoHS Compliant Product: Restriction of the u of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. The substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Product Type Speed Code –3S
–3.7
Unit Speed Grade PC2–5300 5–5–5
PC2–4200 4–4–4—max. Clock Frequency
@CL5f CK5333266MHz @CL4f CK4266266MHz @CL3
f CK3200200MHz min. RAS-CAS-Delay t RCD 1515ns min. Row Precharge Time t RP 1515ns min. Row Active Time t RAS 4545ns min. Row Cycle Time
t RC
60
60三才是指什么
ns
HYS72T[64/128/256]4[00/20]HFD–[3S/3.7]–A
1.2Description
This document describes the electrical and mechanical features of a 240-pin, PC2-4200F, PC2-5300F ECC type,Fully Buffered Double-Data-Rate Two Synchronous DRAM Dual In-Line Memory Modules (DDR2 SDRAM FB-DIMMs).Fully Buffered DIMMs u commodity DRAMs isolated from the memory channel behind a buffer on the DIMM. They are intended for u as main memory when installed in systems such as rvers and workstations. PC2-4200, PC2-5300refers to the DIMM nam
ing convention indicating the DDR2SDRAMs running at 266, 333MHz clock speed and offering 4200, 5300MB/s peak bandwidth. FB-DIMM features a novel architecture including the Advanced Memory Buffer. This single chip component, located in the center of each DIMM,acts as a repeater and buffer for all signals and commands which are exchanged between the host controller and the DDR2 SDRAMs including data in- and output. The AMB communicates with the host controller and / or the adjacent
DIMMs on a system board using an Industry Standard High-Speed Differential Point-to-Point Link Interface at 1.5 V.
The Advanced Memory Buffer also allows buffering of memory traffic to support large memory capacities. All memory control for the DRAM resides in the host, including memory request initiation, timing, refresh, scrubbing, sparing,configuration access, and power management. The Advanced Memory Buffer interface is responsible for handling channel and memory requests to and from the local DIMM and for forwarding requests to other DIMMs on the memory channel. Fully Buffered DIMM provides a high memory bandwidth, large capacity channel solution that has a narrow host interface. The maximum memory capacity is 288 DDR2SDRAM devices per channel or 8 DIMMs.
TABLE 2
Ordering Information (Pb-free components and asmbly)
Product Type 1)
1)All product types end with a place code, designating the silicon die revision. Example: HYS 72T64000HFA-3.7-A, indicating Rev. A dice
are ud for DDR2 SDRAM components. To learn more on QIMONDA DDR2 module and component nomenclature e ction 8 of this datasheet.
Compliance Code 2)
2)The Compliance Code is printed on the module label and describes the speed grade, e.g. “PC2-4200F-444-11-A”, where 4200F means
Fully Buffered DIMM with 4.26 GB/c. Module Bandwidth and “444-11” means CAS latency = 4, t rcd latency = 4 and t rp latency = 4 using JEDEC SPD Revision 1.1 and asmbled on Raw Card “A”.
Description
SDRAM Technology
PC2-4200F (DDR2-533):HYS72T64400HFD–3.7–A 512MB 1R ×8PC2–4200F–444–11–A 1 Rank, FB-DIMM 512Mbit (×8)HYS72T128420HFD–3.7–A 1GB 2R ×8PC2–4200F–444–11–B 2 Ranks, FB-DIMM 512Mbit (×8)HYS72T256420HFD–3.7–A 2GB 2R ×4PC2–4200F–444–11–H
2 Ranks, FB-DIMM
512 Mbit (×4)
PC2-5300F (DDR2-667):HYS72T64400HFD–3S–A 512MB 1R ×8PC2–4200F–444–11–A 1 Rank, FB-DIMM 512Mbit (×8)HYS72T128420HFD–3S–A PC2–4200F–444–11–B
2 Ranks, FB-DIMM 512Mbit (×8)HYS72T256420HFD–3S–A
2GB 2R ×4PC2–4200F–444–11–H
2 Ranks, FB-DIMM
庵埠中学512 Mbit (×4)
HYS72T[64/128/256]4[00/20]HFD–[3S/3.7]–A
TABLE 3
Address Format
TABLE 4
Components on Modules
DIMM Density Module
Organization Memory Ranks ECC/Non-ECC # of
SDRAMs # of row/bank/columns bits Raw Card 512MB 64M ×721ECC 913/2/10A 1GB 128M ×722ECC 1813/2/10B 2GB
256M ×72
2
ECC
36
13/2/11
H
Product Type DRAM components 1)1)Green Product
DRAM Density DRAM Organisation Note 2)
2)For a detailed description of all functionalities of the DRAM components on the modules e the component datasheet.
HYS72T64000HF HYB18T512800AF 512Mbit 64M ×8HYS72T128020HF HYB18T512800AF 512Mbit 64M ×8HYS72T256020HF
HYB18T512400AF
512Mbit
128M ×4
HYS72T[64/128/256]4[00/20]HFD–[3S/3.7]–A 2Pin Configuration
The pin configuration of the DDR2 SDRAM DIMM is listed by function in Table5 (240 pins). The abbreviations ud in columns Pin and Buffer Type are explained in Table6 and Table7 respectively. The pin numbering is depicted in Figure1.
TABLE5
Pin Configuration of FB-DIMM
Pin#Name Pin
Type Buffer
Type
Function
Clock Signals
228SCK I HSDL_15System Clock Input, positive line
229SCK I HSDL_15System Clock Input, negative line Control Signals
17RESET I LV-CMOS AMB ret signal
Northbound
22PN0O HSDL_15Primary Northbound Data, positive lines 25PN1O HSDL_15
28PN2O HSDL_15
31PN3O HSDL_15
34PN4O HSDL_15
37PN5O HSDL_15
51PN6O HSDL_15
绿色公益
54PN7O HSDL_15
57PN8O HSDL_15
60PN9O HSDL_15
63PN10O HSDL_15
66PN11O HSDL_15
48PN12O HSDL_15
40PN13O HSDL_15
23PN0O HSDL_15
读书笔记一千字26PN1O HSDL_15
29PN2O HSDL_15
32PN3O HSDL_15
七字词语35PN4O HSDL_15
38PN5O HSDL_15
52PN6O HSDL_15
55PN7O HSDL_15
58PN8O HSDL_15法人身份证明书
61PN9O HSDL_15
64PN10O HSDL_15
