Equalizer circuitry for mitigating pre-cursor and

更新时间:2023-07-30 14:14:45 阅读: 评论:0

专利名称:Equalizer circuitry for mitigating pre-cursor
and post-cursor intersymbol interference为途
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发明人:Timothy M. Hollis住酒店注意事项
申请号:US11866813
申请日:20071003
公开号:US07869494B2
公开日:
20110111
专利内容由知识产权出版社提供
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专利附图:熟悉的英语
摘要:One or more embodiments of the invention compri a continuous-time松辽平原
equalizer (CTE) for reducing both pre-cursor and post-cursor intersymbol interference (ISI) from data received from a communication channel. One such equalizer compris two
independent stages that process the input signal in parallel. One stage subtracts a scaled version of the derivative of the input signal from a scaled version of the input signal to reduce pre-cursor ISI from the input signal. The other stage adds a scaled version of the derivative of the input signal to a scaled version of the input signal to reduce post-cursor ISI from the input signal. The outputs from the two stages are then multiplied to arrive at an output signal in which both pre- and post-cursor ISI is minimized. Becau the scalars ud in each of the stages are independent, each can be adjusted for greater manipulation of the ISI-reduced signal.
申请人:Timothy M. Hollis
地址:Meridian ID US
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国籍:US
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代理机构:Wong, Cabello, Lutsch, Rutherford & Brucculeri, LLP
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