谭璇
ENA INA GND INB
ENB OUTA VDD OUTB
Dual Inverting Inputs
ENA INA GND INB
ENB OUTA VDD OUTB
招聘启示还是启事
Dual Non-Inverting Inputs
ENA INA GND INB
ENB OUTA VDD OUTB
One Inverting and One Non-Inverting Input
INA-
INB-GND OUTB
INA+
INB+OUTA VDD
Dual Input Configuration
UCC27523,UCC27524,UCC27525,UCC27526
ZHCS502F –NOVEMBER 2011–REVISED MAY 2013
双5A 高速低侧栅极驱动器
查询样品:UCC27523,UCC27524,UCC27525,UCC27526
特性
应用范围
•工业标准引脚分配
•开关模式电源
•两个独立的栅极驱动通道•直流(DC)到DC 转换器•5A 峰值驱动源电流和灌电流•电机控制，太阳能
•针对每个输出的独立使能功能
•
用于诸如GaN 等新上市的宽带隙电源器件的栅极驱动器
•与电源电压无关的TTL 和CMOS 兼容逻辑阀值•针对高抗扰度的滞后逻辑阀值
说明
•
输入和使能引脚电压电平不受VDD 引脚偏置电源UCC2752x 系列器件是双通道、高速、低侧栅极驱动电压限制
器，此器件能够有效地驱动MOSFET 和绝缘栅极型功• 4.5V 至18V 单电源范围
率管(IGBT)电源开关。使用能够从内部大大降低击穿•在VDD 欠压闭锁(UVLO)期间，输出保持低电电流的设计，UCC2752x 能够将高达5A 拉电流和5A 平，（以确保加电和断电时的无毛刺脉冲运行）灌电流的高峰值电流脉传送到电容负载，此器件还具有•快速传播延迟（典型值13ns ）
轨到轨驱动能力和典型值为13ns 的极小传播延迟。•快速上升和下降时间（典型值7ns 和6ns ）除此之外，此驱动器特有两个通道间相匹配的内部传播•两通道间典型值为1ns 的延迟匹配时间延迟，这一特性使得此驱动器非常适合于诸如同步整流•针对更高的驱动电流，两个输出可以并联器等对于双栅极驱动有严格计时要求的应用。这还使•当输入悬空时输出保持在低电平
得两个通道可以并连，以有效地增加电流驱动能力或者•
环氧树脂双列直插式(PDIP)-8，小外形尺寸集成电使用一个单一输入信号驱动两个并联在一起的开关。路(SOIC)-8，表面贴装小外形尺寸(MSOP)-8封装PowerPAD™和3mm x 3mm 超薄型小外形尺寸输入引脚阀值基于TTL 和CMOS 兼容低压逻辑，此逻(WSON)-8封装选项
辑是固定的并且与VDD 电源电压无关。高低阀值间•
-40°C 至+140°C 的运行温度范围
的宽滞后提供了出色的抗扰度。
产品矩阵
Plea be aware that an important notice concerning availability,standard warranty,and u in critical applications of Texas Instruments miconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
UCC27523,UCC27524,UCC27525,UCC27526
ZHCS502F–NOVEMBER2011–REVISED
这些装置包含有限的内置ESD保护。
存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止MOS门极遭受静电损伤。
说明（继续）
UCC2752x系列产品提供了三个标准逻辑选项的组合-双路反相，双路非反相，一路反相和一路非反相驱动器。UCC27526特有一个双输入设计，此设计为每个通道提供了反相（IN-引脚）和非反相（IN+引脚）配置的灵活性。IN+或IN-引脚中的任何一个控制驱动器输出状态。未使用的输入引脚可被用于启用和禁用功能。出于安全的考虑，UCC2752x系列内所有器件输入引脚上的内部上拉和下拉电阻器可在输入引脚处于悬空条件下时确保输出保持低电平。为了能够更好地控制驱动器应用的运行，UCC27323，UCC27324和UCC27325均特有一个使能引脚（ENA和ENB）。针对高电平有效逻辑，这些引脚被内部上拉至VDD并可针对标准运行而保持断开。
UCC2752x系列器件采用SOIC-8(D)，带有外露焊垫的MSOP-8(DGN)和带有外露焊垫的3mm x3mm WSON-
8(DSD)封装。UCC27524也可采用PDIP-8(P)封装。对于UCC27526，只提供3mm x3mm WSON(DSD)封装。
ORDERING INFORMATION(1)(2)
PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE,T A
SOIC8-Pin(D),MSOP8-pin(DGN),
UCC27523
WSON8-pin(DSD)
SOIC8-Pin(D),MSOP8-pin(DGN),
UCC27524
WSON8-pin(DSD),PDIP8-pin(P)-40°C to140°C
SOIC8-Pin(D),MSOP8-pin(DGN),
UCC27525
WSON8-pin(DSD)
UCC27526WSON8-pin(DSD)
(1)For the most current package and ordering information,e Package Option Addendum at the end of this document.
(2)All packages u Pb-Free lead finish of Pd-Ni-Au which is compatible with MSL level1at255°C to260°C peak reflow temperature to be
compatible with either lead free or Sn/Pb soldering operations.DSD package is rated MSL level2.
TOPSIDE MARKING INFORMATION
PART NUMBER WITH PACKAGE DESIGNATOR TOP MARKINGS
UCC27524D27524
UCC27524DGN27524
UCC27524DSD SBA
UCC27524P27524
UCC27523D27523
UCC27523DGN27523
UCC27523DSD27523
UCC27525D27525
UCC27525DGN27525
UCC27525DSD27525
UCC27526DSD SCB
UCC27523,UCC27524,UCC27525,UCC27526 ZHCS502F–NOVEMBER2011–REVISED MAY2013
ABSOLUTE MAXIMUM RATINGS(1)(2)爱在细微处600字作文>炒虾的家常做法
over operating free-air temperature range(unless otherwi noted)
MIN MAX UNIT Supply voltage range VDD-0.3to20.0
DC-0.3to VDD+0.3V OUTA,OUTB voltage
Repetitive pul<200ns(3)-2.0to VDD+0.3
Output continuous source/sink
I OUT_DC0.3
current
天上风筝在天上飞
A Output puld source/sink current
I OUT_puld5
(0.5µs)
INA,INB,INA+,INA-,INB+,INB-,ENA,ENB voltage(4)-0.320
Human body model,HBM4000V ESD(5)
Charge device model,CDM1000
Operating virtual junction temperature,T J range-40150
Storage temperature range,T stg-65150
°C
Soldering,10c.300
Lead temperature
Reflow260
(1)Stress beyond tho listed under absolute maximum ratings may cau permanent damage to the device.The are stress ratings
only and functional operation of the device at the or any other conditions beyond tho indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)All voltages are with respect to GND unless otherwi noted.Currents are positive into,negative out of the specified terminal.See
Packaging Section of the datasheet for thermal limitations and considerations of packages.
(3)Values are verified by characterization on bench.
(4)The maximum voltage on the Input and Enable pins is not restricted by the voltage on the VDD pin.
(5)The devices are nsitive to electrostatic discharge;follow proper device handling procedures.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range(unless otherwi noted)
MIN TYP MAX UNIT Supply voltage range,VDD 4.51218V Operating junction temperature range-40140°C
Input voltage,INA,INB,INA+,INA-,INB+,INB-018V Enable voltage,ENA and ENB018
UCC27523,UCC27524,UCC27525,UCC27526
ZHCS502F–NOVEMBER2011–REVISED
THERMAL INFORMATION
UCC27523,UCC27523,
UCC27524,UCC27524,
UCC27525UCC27525
THERMAL METRIC UNITS
SOIC(D)MSOP(DGN)(1)
8PINS8PINS
θJA Junction-to-ambient thermal resistance(2)130.971.8
θJCtop Junction-to-ca(top)thermal resistance(3)80.065.6
θJB Junction-to-board thermal resistance(4)71.47.4
°C/W
ψJT Junction-to-top characterization parameter(5)21.97.4
ψJB Junction-to-board characterization parameter(6)70.931.5
θJCbot Junction-to-ca(bottom)thermal resistance(7)n/a19.6
(1)For more information about traditional and new thermal metrics,e the IC Package Thermal Metrics application report,SPRA953.
(2)The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard,high-K board,as好男人面相
specified in JESD51-7,in an environment described in JESD51-2a.
(3)The junction-to-ca(top)thermal resistance is obtained by simulating a cold plate test on the package top.No specific JEDEC-
standard test exists,but a clo description can be found in the ANSI SEMI standard G30-88.
(4)The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature,as described in JESD51-8.
(5)The junction-to-top characterization parameter,ψJT,estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtainingθJA,using a procedure described in JESD51-2a(ctions6and7).
(6)The junction-to-board characterization parameter,ψJB,estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtainingθJA,using a procedure described in JESD51-2a(ctions6and7).
(7)The junction-to-ca(bottom)thermal resistance is obtained by simulating a cold plate test on the expod(power)pad.No specific
JEDEC standard test exists,but a clo description can be found in the ANSI SEMI standard G30-88.
THERMAL INFORMATION
UCC27524UCC27523,
UCC27524,
UCC27525,
THERMAL METRIC UNITS
UCC27526
PDIP(P)WSON(DSD)(1)
8PINS8PINS
θJA Junction-to-ambient thermal resistance(2)62.146.7
θJCtop Junction-to-ca(top)thermal resistance(3)52.746.7
θJB Junction-to-board thermal resistance(4)39.122.4
°C/W
ψJT Junction-to-top characterization parameter(5)31.00.7
ψJB Junction-to-board characterization parameter(6)39.122.6
θJCbot Junction-to-ca(bottom)thermal resistance(7)n/a9.5
(1)For more information about traditional and new thermal metrics,e the IC Package Thermal Metrics application report,SPRA953.
(2)The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard,high-K board,as
specified in JESD51-7,in an environment described in JESD51-2a.
(3)The junction-to-ca(top)thermal resistance is obtained by simulating a cold plate test on the package top.No specific JEDEC-
standard test exists,but a clo description can be found in the ANSI SEMI standard G30-88.
(4)The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature,as described in JESD51-8.
(5)The junction-to-top characterization parameter,ψJT,estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtainingθJA,using a procedure described in JESD51-2a(ctions6and7).
(6)The junction-to-board characterization parameter,ψJB,estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtainingθJA,using a procedure described in JESD51-2a(ctions6and7).
(7)The junction-to-ca(bottom)thermal resistance is obtained by simulating a cold plate test on the expod(power)pad.No specific
JEDEC standard test exists,but a clo description can be found in the ANSI SEMI standard G30-88.
UCC27523,UCC27524,UCC27525,UCC27526 ZHCS502F–NOVEMBER2011–REVISED MAY2013
ELECTRICAL CHARACTERISTICS
邱笑秋
V DD=12V,T A=T J=-40°C to140°C,1-µF capacitor from V DD to GND.Currents are positive into,negative out of the specified terminal(unless otherwi noted,)
PARAMETER TEST CONDITION MIN TYP MAX UNITS Bias Currents
VDD=3.4V,
INA=VDD,55110175 Startup current,INB=VDD
I DD(off)(bad on UCC27524InputμA
VDD=3.4V,
configuration)
INA=GND,2575145
INB=GND
Under Voltage LockOut(UVLO)
T J=25°C 3.91 4.20 4.50
V ON Supply start threshold
T J=-40°C to140°C 3.70 4.20 4.65
V Minimum operating voltage
V OFF 3.40 3.90 4.40 after supply start
VDD_H Supply voltage hysteresis0.200.300.50
Inputs(INA,INB,INA+,INA-,INB+,INB-),UCC2752X(D,DGN,DSD)
Output high for non-inverting input pins
V IN_H Input signal high threshold 1.9 2.1 2.3
Output low for inverting input pins
Output low for non-inverting input pins V
V IN_L Input signal low threshold 1.0 1.2 1.4
文源阁Output high for inverting input pins
V IN_HYS Input hysteresis0.700.90 1.10
INPUTS(INA,INB,INA+,INA-,INB+,INB-)UCC27524P ONLY
Output high for non-inverting input pins
V IN_H Input signal high threshold 2.3
Output low for inverting input pins
Output low for non-inverting input pins V
V IN_L Input signal low threshold 1.0
Output high for inverting input pins
V IN_HYS Input hysteresis0.9
Enable(ENA,ENB)UCC2752X(D,DGN,DSD)
V EN_H Enable signal high threshold Output enabled 1.9 2.1 2.3
V EN_L Enable signal low threshold Output disabled0.95 1.15 1.35V
V EN_HYS Enable hysteresis0.700.95 1.10
ENABLE(ENA,ENB)UCC27524P ONLY
V EN_H Enable signal high threshold Output enabled 2.3
V EN_L Enable signal low threshold Output disabled0.95V
V EN_HYS Enable hysteresis0.95
Outputs(OUTA,OUTB)
I SNK/SRC Sink/source peak current(1)C LOAD=0.22µF,F SW=1kHz±5A
V DD-V OH High output voltage I OUT=-10mA0.075
V
V OL Low output voltage I OUT=10mA0.01
R OH Output pullup resistance(2)I OUT=-10mA 2.557.5Ω
R OL Output pulldown resistance I OUT=10mA0.150.51ΩSwitching Time
(1)Ensured by design.
(2)R OH reprents on-resistance of only the P-Channel MOSFET device in pullup structure of UCC2752X output stage.
