SAN JOSE STATE UNIVERSITY
College of Engineering
DEPARTMENT OF ELECTRICAL ENGINEERING
EE271
Tutorial on Using Synopsys Verilog Compiler Simulator This tutorial basically describes how to u the Synopsys Verilog Compiler Simulator (vcs) to simulate a Verilog description of a design and how to display graphical waveforms.
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If you already have an account on Cadence lab then u it. There is no need for having multiple accounts. If you’re an engineering student or are taking an engineering class, you already have one UNIX account. You can (re)t your password by following the instruction sjsu.edu
Once you have already had an account, you can login to your account from workstations in room ENGR289 and room ENGR291. You can remote login to your account from you PC by using SSH remote Secure Shell together with the X-Server for Window software, the Exceed Hummingbird.
The Synopsys VCS Simulator
VCS (Verilog Compiler Simulator) is a tool suite from Synopsys. It includes VirSim, a graphical ur interface to VCS for debugging and viewing waveforms.
The methodology of debugging your project design involves three steps:
1) Compiling your verilog source code,
2) Running the simulation, and
3) Viewing the generated waveforms.
The VCS tools will allow you to combine the steps to debug your design interactively. VCS works by compiling your Verilog source code into object files, or translating them into C source files. VCS invokes a C compiler (cc, gcc, or egcs) to create an executable file that will simulate your design. This simulator can be executed on the command line, and can create a waveform file. Alternately, the design can be simulated interactively using VirSim, and the waveforms can be viewed as you step through the simulation.
The rest of this document will give a brief overview of the tools and show you how to compile and simulate a down-counter example.
特殊英文Initial Setup
The VCS package is installed at /apps/synopsys/X-2005.06-SP2/bin/vcs. For convenience, t the following environment variables to your .cshrc file. Remember that anytime you changed/modified .cshrc file, you must source it (by command “source .cshrc”) or by logging-out and then logging back in.
tenv MYPATH $PATH
tenv SYNOPSYS /apps/synopsys
tenv SNPSLMD $SYNOPSYS/Y-2006.06-SP1
tenv VCS_ARCH_OVERRIDE redhat30庆祝
tenv SYNOPSYS_SIM $SYNOPSYS/X-2005.06-SP2
tenv CLS_CSD_COMPATIBILITY_LOCKING NO
tenv SKIP_CDS_DIALOG
tenv VCS_HOME $SYNOPSYS_SIM
t path=($path $SNPSLMD/linux/bin )
t path=($path $SYNOPSYS )
t path=($path $SYNOPSYS/Y-2006.06-SP1/linux/syn/bin )西安洛阳
source $SYNOPSYS_SIM/bin/environ.csh
五月天瑟瑟
Create a directory where you want to do the tutorial and create the following three text files named count.v, test_count.v, and main_count.f in that directory. Listings of count.v and test_count.v are at the end of this tutorial. The main_count.f file has only 1 line as shown below:
test_count.v count.v
Compiling and Simulating in post-processing mode
1. Change to tutorial directory that contains count.v, test_count.v, and
main_count.f (in this tutorial it is tutorial)
2. Compile the verilog source code by typing the following at the machine prompt
/export/home/staff/thuyle/tutorial> vcs -f main_count.f option means that the file specified (
九江面积-f main_count.f
The ) contains a list of command line options for vcs. In this ca, the command-line options are just a list of file names and note that the testbench is listed first. The following command line would have the same effect:
服务密码初始密码/export/home/staff/thuyle/tutorial> vcs test_count.v count.v
/export/home/staff/thuyle/tutorial> vcs -f main_count.f
Chronologic VCS (TM)
Version X-2005.06-SP2 -- Wed Oct 11 20:20:03 2006
Copyright (c) 1991-2005 by Synopsys Inc.
ALL RIGHTS RESERVED
This program is proprietary and confidential information of Synopsys Inc.
and may be ud and disclod only as authorized in a licen agreement controlling such u and disclosure.
Parsing design file 'test_count.v'
Parsing design file 'count.v'
Top Level Modules:
test_count
No TimeScale specified
Starting vcs
1 module and 0 UDP read.
recompiling module test_count
if [ -x ../simv ]; then chmod -x ../simv; fi
g++ -o ../simv -melf_i386 -m32 5NrI_d.o 5NrIB_d.o wx0S_1_d.o SIM_l.o /apps/synopsys/X-2005.06-SP2/redhat30/lib/libvirsim.a /apps/synopsys/X-2005.06-SP2/redhat30/lib/libvcsnew.so /apps/synopsys/X-2005.06-SP2/redhat30/lib/ctype-stubs_32.a -ldl -lc -lm -ldl
/usr/bin/ld: warning: libstdc++.so.5, needed by /apps/synopsys/X-2005.06-SP2/redhat30/lib/libvcsnew.so, may conflict with libstdc++.so.6
../simv up to date
CPU time: .053 conds to compile + .226 conds to link
You should now have an executable file called in your working directory.
simv
3. Execute simv on the command line with no arguments. You should e output
from both vcs and the simulation and it should produce a waveform file called count.dump in your working directory.
/export/home/staff/thuyle/tutorial> simv
寒衣Chronologic VCS simulator copyright 1991-2005
Contains Synopsys proprietary information.
Compiler version X-2005.06-SP2; Runtime version X-2005.06-SP2; Oct 11 20:24 2006
$finish at simulation time 136
V C S S i m u l a t i o n R e p o r t
Time: 136
CPU Time: 0.040 conds; Data structure size: 0.0Mb
Wed Oct 11 20:24:53 2006
/export/home/staff/thuyle/tutorial>
4. We are now going to re-invoke vcs to view the waveform. At the prompt, type:
/
export/home/staff/thuyle/tutorial> vcs -RPP count.v
/export/home/staff/thuyle/tutorial> vcs -RPP count.v
VirSim X-2005.06-SP1-12 Virtual Simulator Environment
Copyright (C) 1993-2005 by Synopsys, Inc.
快乐星猫舞蹈Licend Software. All Rights Rerved.
U "virsim [help_arg]" for usage information.
help_arg: -help or -verilog_help or -vhdl_help or -epic_help
-RPP
The option tells vcs that we are opening it in post-processing mode. This should open up a new window as below:
5. In this window, click on open under the File menu option. Change the file type that
you want to open to VCD (not VCD+). (VCD has .dump file extension and VCD+ has .vcd file extension). They are both waveform files but VCD files are text files, and VCD+ are condend binary files.
count.dump
6. Select and open the file and then click OK (also click O.K. on the
information pop-up screen). Click on the test_count button, and you should e all signals instantiated in the signal window: clock, dec, in[3:0],load, and
zero.
