VCS编译xilinxIP核
⽬录
1. 背景
vivado2018.03
vcs O-2018.09-SP2
2. 出现的问题
2.1 vivado编译IP库时显⽰版本不对
ERROR: [Vivado 12-4686] Simulator version check command failed:"/home/fpga-0/software/synopsys2018/vcs_2018.09/bin/vlogan -ID -full64". Plea mak e sure that this version of simulator support the options specified in this command. For more details on this failure, open the '.cxl.vcs_mx.version' file. ERROR: [Vivado 12-4688] Unsupported simulator version. Plea run 'compile_simlib -help' for the supported 'vlogan script version' version.
解决⽅案：
1. 确实是版本不匹配，我的vcs版本⼀开始是2016.06，他就不⽀持Vivado2018.03
厨房里的秘密>形容动物的词语2. ⽤命令⾏开启vivado，这是在⽹上查出来⼀个说开启管理员模式解决了这个问题。我⼀开始是通过点击Vivado图标的⽅式启动的，但
是⼀直报版本不匹配这个问题，最后通过命令⾏启动，这个问题解决了
2.2 vhdlan编译⼀直报错
ERROR - can't find /home/fpga-0/software/synopsys2018/vcs_2018.09/linux/bin/vhdlan1, check installation.
exiting ...
这个问题是vhdlan使⽤⽅法错误，如果安装的是linux64的版本，在使⽤vhdlan时⼀定要加上-full64的参数
2.3 编译报错undefined identifier
Error-[OVNOSELECT1_LIB] Undefined identifier
/
home/fpga-0/NGS_prj/UVM/matrix7_uvm/rtl/lib/lf_iplib/fifo_512x512.vhd, 57
FIFO_512X512
USE fifo_generator_v13_2_3.fifo_generator_v13_2_3;
^
The symbol named 'FIFO_GENERATOR_V13_2_3' cannot be found in library
'FIFO_GENERATOR_V13_2_3'.
Error-[IEEEVHDLNOENT] Missing compiled design unit太息
/home/fpga-0/NGS_prj/UVM/matrix7_uvm/rtl/lib/lf_iplib/fifo_512x512.vhd, 74
analysis-Parsing, "FIFO_512X512"
ARCHITECTURE fifo_512x512_arch OF fifo_512x512 IS
^
猪蹄子的做法The compiled design unit for entity 'FIFO_512X512' is not found in WORK
library.
这个问题⽬前还没有解决，⾸先我已经把synopsys_sim.tup⽂件复制到脚本所在的⽂件夹下了，并且我编译加法器和减法器的.vhd⽂件是没有报错的，.tup⽂件是起了作⽤的。这是.tup⽂件下的IP映射
狮子女和天蝎男fifo_generator_v13_2_3 : /home/fpga-
0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3
这是该路径下的IP编译的库
青霉素v钾胶囊
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/.cxl.verilog.fifo_generator_v13_2_3.fifo_gene rator_v13_2_d
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/.cxl.verilog.fifo_generator_v13_2_3.fifo_gene rator_v13_2_f
农技推广/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/.cxl.verilog.fifo_generator_v13_2_3.fifo_gene rator_v13_2_3.lin64.rpt
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/.cxl.vhdl.fifo_generator_v13_2_3.fifo_generat or_v13_2_d
秋天的景物/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/.cxl.vhdl.fifo_generator_v13_2_3.fifo_generat or_v13_2_f
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/.cxl.vhdl.fifo_generator_v13_2_3.fifo_generat or_v13_2_3.lin64.rpt
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/64
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/64/.vhdl_lib_lock
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/64/vhdl.sdb
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/64/vhmra.sdb
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/.vcs_lib_lock
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/AllModulesSkeletons.sdb
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/compat.db
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/debug_dump
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/dumpcheck.db
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/dve.sdb
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/make.vlogan
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/modfilename.db
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/str.db
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/str.index.db
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/str.info.db
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/vir.sdb
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/vir_global.sdb
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/vloganopts.db
⽬前这个问题还没有解决，我在xilinx社区上提了⼀下遇到的问题，可以确定的是tup⽂件是起了作⽤的，IP库我看了⼀下也是确定编译正确0error和0warning的，⽬前想不出可能哪⾥出现了问题，先总结成这样吧。
