Design Compiler 综合脚本
常用命令和模板
参照自己的设计，以及自己的工艺信息，适当修改下面的Constraints 和 Run Script 等的脚本，添加一些相关的约束语句，就可以运行了
长期待摊费用>短信z详细的命令请参照DC的官方Ur Guide等相关资料。
Invoking Design Compiler
Unix% design_vision # Interactive GUI, WLM mode
Unix% design_vision –topographical # Interactive GUI, Topographical mode
Unix% dc_shell-t # Interactive shell, WLM mode
Unix% dc_shell-t –topographical # Interactive shell, Topographical mode
Unix% dc_shell-t –l | tee –i my.log # Batch mode
.synopsys_dc.tup
t arch_path “$arch_path libs cons unmapped rtl”
t synthetic_library dw_foundation.sldb
t target_library 65nm.db
t link_library “* $target_library $synthetic_library IP.db”
t symbol_library 65nm.sdb
define_design_lib WORK –path ./work
t_svf <my_filename.svf>
t_vsdc <my_filename.vsdc>
history keep 200
t sh_enable_page_mode fal
t cache_write .
t cache_read $cache_write
江西旅游景点suppress_message {LINT-28 LINT-32 LINT-33 UID-401}
t alib_library_analysis_path [get_unix_variable HOME]
alias h history
alias rc “report_constraint -all_violators”
TCL Commands and Constructs夏常青
t PER 2.0 # Define a variable and its value
echo $PER # Variable substitution undefined 2.0
t MARG 0.95
expr $PER * $MARG # expr: *, /, +, -, >, <, =, <=, >=
t pci_ports [get_ports A] # Imbedded command
t pci_ports [get_ports “Y??M Z*”] # Wildcards
诸葛亮是怎么死的echo “Effctv P = \ # Soft quotes undefined 1.9
[expr $PERIOD * $MARGIN]”
echo {Effctv P = \ # Hard quotes
[expr $PERIOD * $MARGIN]} # undefined Effctv P = [expr $PER * $MARG]
# Comment line
t COMMENT in_line; # In-line comment
t MY_DESIGNS {B1.v ... B26.v} # foreach loop
foreach DESIGN $MY_DESIGNS {
read_verilog $DESIGN
我的水蜜桃}
for {t i 1} {$i < 27} {incr i} { # for loop
read_verilog BLOCK_$i.v
}
Helpful UNIX-like DC-shell commands
pwd
cd
ls
history
!!
!7
!report
sh <UNIX_command>
printenv
get_unix_variable ARCH
Constraints
ret_design
t_max_area 0
create_clock -period 2 –name Main_Clk [get_ports Clk1]
create_clock –period 2.5 –waveform {2 3.5} [get_ports Clk2]
create_clock –period 3.5 –name V_Clk; # VIRTUAL clock
t_clock_uncertainty –tup 0.14 [get_clocks *]
t_clock_uncertainty –tup 0.21 –from [get_clocks Main_Clk] –to [get_clocks Clk2]
t_clock_latency –max 0.6 [get_clocks Main_Clk]
t_clock_latency –source –max 0.3 [get_clocks Main_Clk]机械租赁合同
t_clock_transition 0.08 [get_clocks Main_Clk]
t_input_delay -max 0.6 -clock Main_Clk [all_inputs]
t_input_delay –max 0.3 –clock Clk2 –clock_fall –add_delay [get_ports “B E”]
太极扇中国功夫
t_input_delay -max 0.5 -clock –network_latency_included V_Clk [get_ports “A C F”]
t_output_delay -max 0.8 -clock –source_latency_included Main_Clk [all_outputs]
t_output_delay -max 1.1 -clock V_Clk [get_ports “OUT2 OUT7]
t_max_capacitance 1.2 [all_inputs]
t_load 0.080 [all_outputs]
t_load [expr [load_of slow_proc/NAND2_3/A] * 4] [get_ports OUT3]
t_load 0.12 [all_inputs]
t_input_transition 0.12 [remove_from_collection [all_inputs][get_ports B]]
t_driving_cell –lib_cell FD1 –pin Q [get_ports B]
t_operating_conditions –max WCCOM
t auto_wire_load_lection fal
t_wire_load_model –name 1.6MGates
t_wire_load_mode enclod
t_wire_load_model –name 200KGates [get_designs “SUB1 SUB2”]
t_wire_load_model –name 3.2MGates [get_ports IN_A]
t_port_fanout_number 8 [get_ports IN_A]
t_fal_path -from [get_clocks Asynch_CLKA] -to [get_clocks Asynch_CLKB]
t_multicycle_path –tup 4 –from –from A_reg -through U_Mult/Out –to B_reg
t_multicycle_path –hold 3 –from –from A_reg -through U_Mult/Out –to B_reg
t_isolate_ports –type inverter [all_outputs]
t_ideal_network [get_ports ret* lect*]
t_ideal_network [get_pins FF_SET_reg/Q]
t_ideal_network –no_propagate [get_nets CTRL]
t_ideal_latency 1.4 [get_ports ret* lect*]
t_ideal_transition 0.5 [get_pins FF_SET_reg/Q]
t_scan_configuration -style <multiplexed_flip_flop | clocked_scan | lssd | aux_clock_lssd>
Checking and Removing Constraints and Directives
report_clock; report_clock -skew
report_design
report_port –verbo
report_wire_load
report_path_groups
report_timing_requirements (–ignored)
report_auto_ungroup
report_isolate_ports
write_script –output &l>
check_timing
ret_path –from FF1_reg
