A1.2-V250-mW14-b100-MS/s Digitally Calibrated Pipeline ADC in90-nm CMOS
Hans Van de Vel,Member,IEEE,Berry A.J.Buter,Hendrik van der Ploeg,Maarten Vertregt,Member,IEEE, Govert J.G.M.Geelen,Member,IEEE,and Edward J.F.Paulus
Abstract—This paper describes a digitally calibrated pipeline
analog-to-digital converter(ADC)implemented in90nm CMOS
technology with a1.2V supply voltage.A digital background cal-
ibration algorithm reduces the linearity requirements in thefirst
stage of the pipeline chain.Range scaling in thefirst pipeline stage
enables a maximal1.6V pp input signal swing,and a charge-ret
switch eliminates ISI-induced distortion.The14b ADC achieves
73dB SNR and90dB SFDR at100MS/s sampling rate and
250mW power consumption.The73dB SNDR performance is
maintained within3dB up to a Nyquist input frequency and the
FOM is0.68pJ per conversion-step.
Index Terms—ADC,analog-to-digital conversion,calibration,
信息化项目
charge ret,CMOS analog integrated circuits,low power,low
voltage,pipeline,range scaling.
I.I NTRODUCTION
R ECENT advances in converter technology have enabled
a cellular ba station receiver to shift its architecture of
choice from a bank of narrowband single-channel receivers to a
single wideband multi-channel receiver,significantly reducing
the cost and complexity of cellular ba stations[1].The key
elements of a wideband multi-channel receiver are a high-res-
olution wide-bandwidth ADC to digitize multiple channels in
a cellular frequency band,and a digital wideband channelizer
to extract the individual channels.Typically the ADC is imple-
mented in a CMOS technology with a high supply voltage[2],
[3].The implementation of the digital channelizer benefits from
the higher density and lower power consumption resulting from
the scaling of CMOS technology,such that the most advanced
CMOS technology with a low supply voltage is ud here.The
next step in the cost reduction of a cellular ba station is to
integrate the ADC and the channelizer on a single CMOS die,
preferably with a single,low supply voltage.
The challenging bandwidth and dynamic range requirements
in a wideband cellular receiver determine the sampling
rate
and the signal-to-noi ratio(SNR)of the ADC,and the blocking characteristics dictate the ADC’s spurious-free dy-namic range(SFDR).For2.5G and3G cellular standards like EDGE and UMTS,an ADC with a sampling rate in the range of 80–150MS/s,an SNR of72–75dB and an SFDR of85–90dB is required.The latter specification however is not sufficient Manuscript received August25,2008;revid November19,2008.Current version published March25,2009.
H.Van de Vel,B.A.J.Buter,M.Vertregt,G.J.G.M.Geelen,and E.J.F. Paulus are with NXP Semiconductors,5656AE Eindhoven,The Netherlands (e-mail:hans.van.de.).
H.van der Ploeg is with Catena Radio Design,5692GA Son en Breugel,The Netherlands.
Digital Object Identifier10.1109/JSSC.2009.2014702for a GSM system where the difference in channel attenuation for near and far urs demands an SFDR of100dB or higher. Furthermore in a highly integrated system,the ADC’s power consumption needs to be low.
A power-efficient architecture for a high-resolution wide-bandwidth ADC is the pipeline ADC architecture[4].The pipelining of the quantizing operation results in a good trade-off between noi,linearity and speed,at the cost of an incread latency.The gain in each pipeline stage relaxes the noi and linearity requirements for the subquent stages,such that the power required for quantization at a certain speed can be scaled down towards the end of the pipeline chain.
In this paper a14b100MS/s ADC is prented that is de-signed in a90nm CMOS technology with a1.2V supply voltage [5].It is suited for embedding in a highly integrated wideband cellular ba station receiver.
This paper is organized as follows.The key techniques and design choices that enable a power efficient high-res-olution wide-bandwidth ADC in nm-CMOS are addresd in Section II.One of the key techniques is a new algorithm for digital background calibration of stage gain nonlinearity, which
is introduced in Section III.The architecture and the circuit-level design details of the converter are discusd in Sections IV and V.Section VI prents the experimental results and Section VII concludes the paper.
II.H IGH-R ESOLUTION W IDE-B ANDWIDTH ADC IN nm-CMOS This ction discuss design choices that enable good power efficiency for high-resolution wide-bandwidth ADCs in nm-CMOS technologies with low supply voltages.Such converters have achieved good power efficiency in CMOS technologies with a minimal gate length of
0.18m and a3V supply voltage[3].Various authors however project an increa in the power consumption in analog circuits with decreasing supply voltages[6],[7].Furthermore the intrinsic transistor voltage
gain decreas with the scaling of CMOS technology,whereas the power efficiency and the density of digital circuits improve.
A sampled-data analog circuit,such as a pipeline ADC,es-ntially is constrained by three factors:noi,linearity and speed.While the noi constraint is a fundamental one,the lim-itations in linearity on the contrary are not fundamental and can be overcome by digital calibration[8].The additional design complexity and the extra power consumption of the digital cal-ibration circuits are justified by the power saving in the analog circuits of the ADC,as will be shown in Section II-A.Fur-thermore the digital calibration circuits benefit from CMOS scaling.Section II-
B then shows that the power consumption in a
0018-9200/$25.00©2009IEEE
Fig.1.General pipeline ADC architecture.
pipeline ADC does not increa with decreasing supply voltage,when it is only limited by the thermal noi and the speed of the circuit elements.
A.Digital Calibration of Nonlinearity
简易画画大全
Fig.1shows a general block diagram of a pipeline ADC,which basically is a chain of pipeline stages,where each stage resolves a certain number of bits and generates a residue that is digitized by the next stages.Each pipeline stage consists of an analog-to-digital sub-converter (ADSC),a sample-and-hold circuit (SH),a digital-to-analog converter (DAC),a subtractor and an amplifier.In CMOS technology the latter four functions usually are combined in a switched-capacitor (SC),multiplying DAC-bad (MDAC)gain stage [9].The dominant limitations in the static linearity of an SC pipeline stage are comparator offt in the ADSC,DAC nonlinearity and stage gain nonlinearity.The effect of comparator offt in the ADSC is mitigated in the digital domain by using over-range codes [4].The increa in conversion range by adding the over-range codes is justified by the power saving in the ADSC.
The static DAC nonlinearity in a pipeline stage is mainly caud by capacitor mismatch.The differential nonlinearity (DNL)due to this capacitor mismatch is inverly proportional to the square ro
ot of the total capacitance value in the DAC [2].
If
for
noi considerations the capacitance values are chon sufficiently high,then often also the DNL requirement is met and no digital calibration is needed to overcome the DAC nonlinearity.
The stage gain nonlinearity is determined by a first-order gain error and a third-order gain compression.The clod-loop
gain
of a typical SC pipeline stage (Fig.1)that
resolves
bits
is
(1)
where
is the open-loop gain of the stage’s opamp,and feedback
factor
is
(2)
where
and are the MDAC’s unit capacitance and the stage’s feedback capacitance respectively,as shown in Fig.1.
When
and is sufficiently high,
then
equals .Since the relative error in capacitance values is small,the first-order relative gain error can be approximated
by
(3)
This equation shows that the first-order gain error is inverly proportional to the opamp’s open-loop
gain .The third-order gain compression is also determined
by
and by the opamp’s output signal
swing
.The third-order harmonic distortion (HD3)due to the input pair’s transconductance is pro-portional
to
squared and inverly proportional
to
squared:
(4)
where is the overdrive voltage of the pair’s transistors.The third-order nonlinearity at the opamp’s output node also
tends to increa
with
.Equations (3)and (4)show that to achieve high linearity,the
opamp’s open-loop
gain needs to be high.For 14b accu-
racy needs to be about 100dB [2].In [3]a single-stage tele-scopic amplifier with gain-boosting is ud becau of its power efficiency.This topology fails in 90nm CMOS due to the low supply voltage and the low intrinsic transistor voltage gain.In [10]a three-stage opamp is ud in 90nm CMOS,but
its
is only 75dB and a three-stage opamp typically is less power ef-ficient becau a lot of power is spent in shifting the non-dom-inant poles to high frequencies for stability.In this work the
V AN DE VEL et al.:A 1.2-V 250-mW 14-b 100-MS/s DIGITALLY CALIBRATED PIPELINE ADC IN 90-nm CMOS
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Fig.2.Calibration block diagram.
stage gain nonlinearity is overcome by a digital background cal-ibration technique,as discusd in Section IV.The additional complexity and power consumption is justified by the power saving in the opamp,which is implemented as a power-efficient
single-stage amplifier with
an
of only 30dB.B.Power Consumption in a Noi-Limited ADC
The power consumption of a noi-limited ADC is propor-tional to the SNR and the sampling
rate:
(5)
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where is the voltage efficiency
and is
the current efficiency [6],
动辄则咎[11],is Boltzmann’s
constant,is the temperature
and is the supply voltage.There is no increa in the power consumption in a noi-limited ADC with decreasing supply voltages,if the product of the voltage and the
current
efficiency
can be maintained constant.In high-resolution wide-bandwidth ADC designs with a 3V supply voltage the single-ended signal swing typically is 1V ,
resulting in a voltage
efficiency
[2].In this work the voltage
efficiency
is maximized by using a range-scaling first stage.Range scaling is effective in reducing the power con-sumption of the stage’s opamp [12],and decouples the choice of the stage’s input and output signal swing,adding an extra de-gree of freedom,as discusd in Section IV.
The main design choices to maximize the current
efficiency are the u of a single-stage opamp in the first stage,as discusd above,and leaving out the dedicated input SHA,as discusd in Section IV.
The design choices which were introduced in this ction and which will be elaborated in next ctions,enable a state-of-the-art power efficiency in a high-resolution wide-bandwidth ADC in nm-CMOS with a supply voltage as low as 1.2V.
III.D IGITAL B ACKGROUND C ALIBRATION A LGORITHM The calibration block diagram is shown in Fig.2.The first stage’s analog residue voltage is digitized by the back-end pipeline chain and fed to the digital post-processing block.The digital correction block implements the inver of the stage gain nonlinearity in the first stage,using a third-order power
ries:
(6)
where the first-and third-order
coefficients
and are the cor-rection parameters.The stage gain nonlinearity is only corrected for the first stage,since for the later stages its effect is suppresd by the preceding gain and the opamps have sufficient open-loop gain.It has been found empirically that the optimal value for the correction
parameter is different from sample to sample,
whereas
for
it is constant.Therefore,
only is iteratively updated by the digital error estimation block (Section III-B),reducing the design complexity of the digital calibration algo-rithm.For decorrelation of the error and the signal,two mode
s of transfer are implemented in the first pipeline stage and con-trolled by the digital post-processing block.The two modes of transfer and their u are discusd in Sections III-A and III-B respectively.The digital encoder block combines the corrected digitized residue,the digital output of the first stage and the mode signal to generate the final 14b output word.A.Two Modes of Transfer
Changing the internal tting of the ADSC and the DAC,as indicated in Fig.2,creates a cond,redundant mode of transfer,as propod in [13].The circuit-level implementation is discusd in Section V-C.Fig.3shows the transfer of the stage’s input signal to its digitized residue,for the two modes of transfer.The mode signal is a binary quence that for each input sample ts the transfer mode and controls the digital en-coder such that the same digital output word is generated for either transfer mode.
The two modes of transfer are ud in a fashion similar to the technique of mixed-signal chopping and calibration of an offt error [14],but now extended to the calibration of the stage gain nonlinearity.The main advantage of the calibration algorithm described here is its improved innsitivity to the amplitude dis-tribution of the ADC’s input signal,becau all output codes contribute to the error estimation as explained next,whereas in [13]the error estimation results from a limited t of output codes.养老院经营模式
B.Background Error Estimation
Fig.4shows the implementation details of the digital correc-tion and error estimation blocks.The background error estima-tion algorithm proceeds in three steps:1)the corrected digitized residue is procesd;2)the procesd signal is integrated;and 3)after a certain number of samples the correction parameter is updated bad on the integrator output.
1050IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.44,NO.4,APRIL 2009
Fig.3.Two modes of transfer.
Fig.4.Digital post-processing block diagram.
Fig.5.Error estimation with the mode signal t to 0.(a)Input signal.(b)Residue signal.(c)Procesd signal.(d)Integrator output.
Fig.5illustrates the error estimation principle,when the mode signal is t to ,the standard transfer mode of the pipeline stage is lected for each sample.A quence of
samples is shown.For clarity of illustration the input
V AN DE VEL et al.:A1.2-V250-mW14-b100-MS/s DIGITALLY CALIBRATED PIPELINE ADC IN90-nm CMOS
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Fig.6.Error estimation with the mode signal a square wave at f=2.(a)Input signal.(b)Residue signal.(c)Procesd signal.(d)Integrator output. signal in Fig.5(a)is a ramp signal,but the error estimation is
designed to be robust to any input signal.The sawtooth-like
residue signal is shown in Fig.5(b),both for an ideal pipeline
stage and one with afirst-order gain error.It can be en that
the error does not have the same sign for each sample.The
processing step
is:
if
if
(7)
resulting in the procesd signal shown in Fig.5(c),where the
error now has the same sign for each sample.After integration,
the signal component in the digitized residue averages out and
the error component is accumulated,as can be en in Fig.5(d).
After a certain number of samples the integrator output is read
out as an estimate of the error,and an update is generated for
the correction parameter.After the update the integrator is ret
for the next iteration.Note that the amplitude of the integrator
output is strongly correlated with the input signal;in fact,it is
piecewi proportional to the integral of the input signal.Espe-
cially when the error is small,the iteration cycle needs to be
prohibitively long for reliable error estimation.
With a proper switching quence between the two modes of
transfer,the error component and the signal component in the
integrator output can be decorrelated,resulting in more robust
and faster error estimation.This is illustrated in Fig.6,where
the mode signal now is a square wave with a frequency
of,
alternatively lecting the standard and the cond,redundant
mode of transfer.The residue signal then toggles between two
sawtooth-like envelopes,shown in Fig.6(b),and the procesd
signal is shown in Fig.6(c).The integrator output in Fig.6(d)
now is less affected by the input signal.
When switching between the two modes of transfer with a
square wave
at,the error and the signal are not effectively
decorrelated for sine wave input signals with a frequency clo
to.The mode signal is therefore implemented as a binary
pudo-random quence of sufficient length[15].
The error estimation algorithm is made robust to non-zero
comparator offts in the ADSC by adding estimates of the com-
parator offt in the condition of(7).The residue is then com-
pared with
code,
where is an offt
estimate for the comparator which determines the transition
of
to.The offts are estimated by monitoring the max-
imum and minimum of the corrected digitized residue for each
value
of.
IV.ADC A RCHITECTURE
Since in a pipeline ADC each stage amplifies a residue
signal,the stage’s requirements in terms of noi and linearity
decrea with the preceding amplification.It is advantageous to
implement a large gain,and hence a large resolution in thefirst
stages[2].The resolution of thefirst pipeline stage is chon
to be4b.This stage is followed by two2.5b stages,ven1.5b
stages and afinal2bflash stage.The design of the back-end
pipeline chain has been reported in[16].In thefirst pipeline
stage,range-scaling decouples the choice of the stage’s input
and output signal swing,such that both can be optimized
parately.With a1.2V supply voltage,the peak-to-peak
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Fig.7.Range-scaling first pipeline stage.
differential input signal swing can be as high as 1.6V.The 0.2V voltage headroom is sufficient for the reference buffers,since the buffers drive a static reference level.The first stage’s opamp and the back-end pipeline chain on the other hand require a larger voltage headroom.The range-scaling first stage therefore reduces the output signal swing with a factor of 2to 0.8V.The voltage
efficiency at the stage’s input and output then is 0.7and 0.3respectively.
Often a dedicated input sample-and-hold amplifier (SHA)is ud such that the input to the first pipeline stage is a sampled-data signal [2].Such an SHA samples wide-bandwidth noi prior to any amplification and its power consumption is dictated by the noi,linearity and speed requirements.In this design no dedicated input SHA is ud to save a significant amount of power.This however pos additional constraints on the first pipeline stage,as will be explained in Section V.
V .C IRCUIT I MPLEMENTATION
A.Range-Scaling First Pipeline Stage
The 4b first pipeline stage is shown in Fig.7(depicting one out of fourteen comparators),with a feedback
capacitance to implement the range-scaling,and a
capacitance to im-plement the two modes of transfer,as explained in Section V-C.
During
pha the charge
in
is ret,and the voltage over sampling
capacitances
and
to tracks the input voltage,which is sampled at the falling edge
of
.During
pha a capacitance
sized and
capacitance are connected in a feedback configuration over the opamp,and the sampling ca-
开心连连
pacitances
to are connected to the reference levels generated by a resistor ladder.Two reference levels for each com-parator can be lected to implement the two modes of transfer
(Section V-C).At the falling edge
of
the differences be-tween the input signal and the reference levels are latched and
the unit capacitances
sized
are either connected to plus or minus the reference voltage.The clod-loop gain then
is
(8)
and the feedback
factor
is
(9)
When
both
and equal zero,(8)and (9)correspond to (1)and (2).The value of feedback
capacitance
is chon such that the clod-loop gain of the 4b stage equals 4.The output signal swing is then reduced with a factor of 2.
As discusd above,the first pipeline stage is not preceded by a dedicated input SHA.The bandwidth and timing mismatch be-tween the sampling operations in the MDAC and in the ADSC then need to be minimized to minimize the aperture error.In the pipeline stage in Fig.7,this aperture error is minimized
by sampling simultaneously at the falling edge
of
and by matching the track pha bandwidth.A similar approach to min-imize the aperture error has been propod recently in [17].With a time-continuous input signal for the first stage,the input switches in Fig.7are jointly bootstrapped to reduce distortion at high frequency and high swing [7].
The opamp in the first pipeline stage is a single-stage ampli-fier with two branches.It us a pMOS input pair with nMOS cascode transistors in the folded branch.The pMOS load transistors are not ca
scoded due to limited voltage headroom.A switched-capacitor common-mode feedback (CMFB)circuit controls the output common-mode level.B.Charge-Ret Switch
Adding
capacitance in the range-scaling first pipeline stage (Fig.7)requires attention to maintain linearity.At the
ont of
pha
the voltage over sampling
capacitance needs to ttle to the instantaneous value of the input voltage.This ttling behavior is characterized by a time
constant
,
where is the output
resistance of the ADC driver
and
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and are the on-resistances of the input switch and the sampling switch respectively.The on-resistance of the switches can be as low as
a few Ohm,
but
typically is
50resulting in slow ttling.This slow ttling caus inter-symbol interference (ISI),where the sampled voltage is related to the previously sampled voltage.For the circuit in Fig.7this relation is nonlinear,
becau a nonlinear part of the sampled charge
in is trans-ferred to feedback
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capacitance ,and is ret in
pha .The ISI then results in distortion.
Implementing a charge-ret switch,as shown in Fig.8,eliminates the ISI and the associated distortion mechanism.The charge-ret switch is on during ret
pha ,and the
sampling
capacitance
is connected to the input signal only after the ret pha,in
pha
.The ttling behavior in the ret pha is characterized
by
,
where is the on-resistance of the charge-ret switch.This ttling is fast and the ret pha can be short.C.Two Modes of Transfer
In the first pipeline stage in Fig.7,the
capacitance and the two reference levels for each comparator are ud to imple-ment the two modes of transfer.Shifting the analog levels in the stage’s ADSC and DAC with half a sub-range creates the cond,redundant mode of transfer.In the resistor ladder-bad
