A Basic Introduction to the g m/I D-Bad Design
Methodology
0.1Abstract
This article introduces the reader to the g m/I D-bad design methodology,which is a way to help CMOS analog circuit designers link physical transistor pa-rameters to small signal models.It is written at the level of university students who are taking afirst cour on analog integrated circuits.It is also rel-evant to experienced engineers interested in a design flow that incorporates technology details early in the design cycle and yields excellent agreement between hand-calculations and circuit simulations.
0.2Introduction
Following perhaps a long road to maturity,CMOS has become an excellent platform for analog circuit design.Not only is it unrivaled in switching and charge-mode processing,but it benefits from persis-tent process improvements fueled by the digital con-sumer market.Unfortunately,designers mayfind it very difficult to take advantage of the strengths.A primary reason for this is that CMOS behavior is hard to predict without using very complex models,and this complexity only worns with technology scal-ing.D
esigners,incidentally under pressure to meet deadlines,are forced to either incorporate complex models into their hand calculations or spiral into a Spice-intensive design loop.Neither of the strate-gies are as effective or pleasant as we would like.
My goal in this article is to introduce you to the g m/I D-bad design methodology,which greatly im-proves the predictability of CMOS small-signal be-havior without requiring complex equations.We will define the ratio g m/I D in more detail later,but for now,just think of it as a design variable that encap-sulates the biasing conditions of a MOS transistor. Or,even more concily:
g m/I D≈bias point small-signal model Development of the methodology will involve veral steps.We will start with a very broad overview of analog circuit design to e what problem it is that we are attemping to solve,and how it has been solved in the past.I will then explain,at a qualitative
level,
Figure1:Low-level circuit implementation is often more difficult than higher-level design.
why the g m/I D-bad approach is the best tool for solving this problem.Next,we will rehash the en-tire discussion at a quantitave level.This will entail a review of transistor operation and a chronological development of the tools we have available.Finally, we will clo with a thorough design example.
0.3The Big Picture
0.3.1Analog Design Relies on Ab-
straction
Fig.1shows veral levels of abstraction in which we can view an analog design.Thanks to abstractions, engineers working at the higher levels can perform analysis using linear Signals-and-Sytems theory.This is the domain offilters,gain blocks,OpAmp circuits, etc.The mathematics that govern this realm are el-egant,often with centuries-old roots.Conquently, we have gotten very good at understanding how to work with the blocks.Most engineering schools nd students throu
gh an entire battery of cours that satisfactorily cover this area.
Descending to the lower levels,there is a different story.While wefind it straightforward to build a gain-of-two stage using an OpAmp,wefind it very difficult to build the OpAmp itlf.How big should each transistor be?How much bias current is needed? The low-level decisions can be unclear,and there are two big reasons why.First,transistor behavior 1
Figure 2:Small-signal model of a transistor.
is nonlinear,and classical Signals-and-Systems anal-ys fall apart when applied to nonlinear systems.Second,technology advancements change the rules of the game faster than we can make them.There are no centuries-old roots here!As a result,we simply do not have a nice t of transistor equations that is both compact enough for hand calculations and accurate enough to match Spice simulations.
0.3.2
Making Low-Level Design Man-ageable We can make low-level design easier if we transform transistors into Signals-and-Systems-friendly devices.As you know,we do this by approximating each tran-sistor with a few ideal elements,collectively referred to as a small-signal model .Fig.2shows a basic and familiar small signal model of a MOSFET.It also highlights the translational role that g m /I D (or its predecessor,V ov ,another biasing variable)plays in the design process.Of cour,the drawback of using small-signal models is that they introduce errors,as all approximations must.But that is far outweighed by the benefits of using Signals-and-Systems tech-niques,without which we would not have concepts like gain,bandwidth,frequency respon,poles,and zeros!
Fig.3,then,is a good illustration of how the g m /I D -bad design methodology fits into the big picture.At the top is the abstract Signals-and-Systems world,where we are very comfortable.At the bottom are physical transistors,which,in the end,must behave the way we want them to.Sitting in the middle of all this is g m /I D ,an intermediate biasing variable that bridges the abstract-to-physical gap very well.Keep this picture in mind as we continue our
discussion.
Figure 3:Small signal models allow us to u tran-sistors in a Signals-and-Systems context.
0.3.3
Why g m /I D is Better than V ov
V ov -bad design,which we will shortly cover in more detail,long predates g m /I D -bad design.As we have
already hinted,both V ov and g m /I D are quantities
that tell you something about the bias point of a tran-sistor.So,how are the approaches different?
When CMOS designers choo to follow a V ov -bad design strategy,they implicitely accept the validity of the long-channel model.I am certain that you are familiar with the long-channel model (we will also review it in a later ction).When we were first taught how to analyze a MOSFET,we were shown a derivation of it using basic calculus.Unfortunately,most of the assumptions that make the derivation so clean are untrue for today’s small geometries.Con-quently,the V ov -bad methodology no longer yields circuits that behave as intended.In order to salvage the model,designers have tried to patch it with short-channel effects and a variety of curve-fitting terms that are (sometimes only wishfully)bad on differ-ent physical arguments.But in the end,V ov -bad design only gets harder and less accurate.
Our new strategy,g m /I D -bad design,does not rely on the validity of the long-channel model.In fact,it does not rely on the validity of anything except simulation.This methodoloy is lookup-table-bad.The underlying philosophy is that the equations gov-erning MOSFETs are so complex that we must get 2
Figure4:High-level comparison of two popular de-sign methodologies.
rid of them in favor of a few tables or graphs.And becau the graphs are generated using device
sim-ulations in Spice,they are much more accurate than the long-channel model could ever hope to be.
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It is no stretch to say that most of us cringe a little at the thought of using a lookup table.With the advent of cheap and powerful computing,we electrical en-gineers have lost touch withfilter tables,log tables, trigonometric tables,and the like.But our current equational exclusivity has been only a brief fad in our industry.Just as vacuum tube circuit designers once ud(and still u!)tube curves,so we are redis-covering the value of table-bad design for situations where it is the most efficient means of”computation.”Fig.4compares V ov-bad design and g m/I D-bad design in a side-by-side summary.In both cas,we need physical information about the technology tar-get.After all,the capabilities of the target will ob-viously affect transistor performance greatly.In the ca of the long-channel model,the technology data must be limited to only the barest of esntials,such asµand C ox,otherwi hand calculations become in-tractible.Conquently,initial designs may only get within an order of magnitude until the designer gets a ”feel”for that process.Meanwhile,the g m/I D-bad method utilizes complete Spice models from the tech-nology target and yields initial results that only re-quire minor tweaking.
0.4The More-Detailed Picture Now I want us to start over trying to solve the design problem,but at a
more quantitative level.We will reach the same conclusion,of cour,even though we are taking a very different approach.
A First Attempt at Transistor-Level Design How might an intelligent-but-inexperienced engineer go about designing a circuit?Of cour,I have a preferred method towards which I am working,but it is certainly worthwhile to e if we can solve the design problem without knowing the answer ahead of time.
To begin,let us step back and ask,what will our finished design look like?Or,what is afinished de-sign?In the context of this article,it is a netlist. Ultimately we just want afile that contains specifica-tions for all the transistors,resistors,capacitors,etc., and explains how they are all connected together.Of cour,in the real world,circuits must be fabricated, and designers must be wary of the limitations of simu-lation itlf,and how well it agrees with actual mea-sured performance,but tho concerns are beyond our scope here.
If our end goal is a netlist,why not start with the netlist and work backwards?What kinds of informa-tion do we need in order to”fill in the blanks?”For reference,here is a line that instantiates a transistor in Hspice:
M1drn gat src blk nchmodel L=0.18u W=10u Well,which blanks can wefill in?Put another way, how do we design a transistor?Obviously,V T,µ,C ox, and other familiar transistor quantities are not among the parameters we get to specify.In fact,apart from the terminal connections,it looks like we only get to choo W and L.
诸葛亮的经典故事Is that all there is to it?Is circuit design just a matter of deciding how big each transistor is?Well,yes and no.With the exception of some advanced options (such as source or drain sharing,or multi-fingered gates),W and L really are the only transistor charac-teristics that you get to explicitely specify.You hook them together,size them correctly,and you almost have the whole thing.Really!
One possible design method,then,might be to just u W and L directly as design variables.This pro-cess would be something like the following:
3
1.Assume you have a usable topology.
2.Guess a bunch of values for W’s and L’s(and
possibly R’s and C’s).
3.Simulate in Spice.
4.See if the design meets all the specifications
青铜葵花好句5.If not,modify W’s and L’s(and possibly R’s and
C’s)and go back to Step3.
Note:This kind of iterative process is some-
times called”Spice Monkeying,”and its u
is strongly discouraged.It is very common
for designers of all experience levels to lap
into Spice Monkeying in the face of looming
deadlines!
This strategy,however tempting,does not work well in practice.First,the sheer length of time required
for simulation makes it impractical to run too many of them(and this is true even if you automate the process).More importantly a Spice-intensive design method is a blind trek,completely devoid of intuition. Spice is good for analyzing a design and makingfinal tweaks,but it is not very good at helping you decide among the infinitude of topologies,sizings,and bias points available in an open-ended task.
All this is summarized in the simplified designflow shown in Fig.5.The inner-most loop,looly called the”hand calculations”pha,is where we have the best opportunities to make big-impact decisions.If we have meaningful and accurate small-signal models, we can make informed and confident decisions in this inner loop without resorting to frequent simulation. Let us e if we can develop a reliable link between small-signal models and actual transistor behavior.
0.4.1Long-Channel Model Review The best vehicle to carry us further on our quanti-tative discussion of MOSFET behavior is the long-channel model.Of cour,I just told you that this model was inadequate,but,just to be clear,I am not advocating its complete abandonment.The deriva-tion may be over-simplified,but it still usually gives the right kind of intuition;and we do not want to be robbed of that.In addition,it is simply a good place to start when discussing transistor modelling.
The long-channel model attempts to describe the re-lationships between drain-current,I D,and the termi-nal voltages,V ds and V gs.The plot in Fig.6is
one
Figure5:We can do more effective optimization in the hand-calculations pha than in the simulations pha of the design process.
of the most commonly ud to display the relation-ships.One thing that is a little different about this plot,compared to others you may have en,is the u of V ov instead of V gs.V ov is called the overdrive voltage,and it is defined as follows:
V ov=V gs−V T
V ov tells you how inverted the channel is,and is a little easier to work with than V gs,in part becau it hides any dependence on V T.Inversion,so-called becau the material in the p-type), starts to behave like the inver type of n-type),can be roughly interpreted as”ON-ness.”It is becau it controls the level of inversion that we can consider V ov to be a biasing variable.Sometimes the condition of having a very small V ov is referred to as weak inversion while a large V ov may cau strong inversion.
Also denoted in Fig.6are the three operating regions: cutoff,linear and saturation.We will quickly go over each one.
Note:This is an N-Channel-centric review.You will have to apply the usualflips to get the P-Channel relationships.
4
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Figure6:In the saturation region,I D is primarily a function of V gs.
CutoffRegion
Condition V ov<0,(or,equivalently,V gs<V T) There is no channel inversion,so no currentflows
I D=0
Linear Region
Condition V ov≥0and V ds<V dsat
There is channel inversion,but I D is heavily affected by V ds
I D=1
2
µC ox
W
L
2V ov V DS−V2DS
The linear region is always of concern when the tran-sistor is being ud as a switch.In that ca,you can also define its ON-resistance.
R on≈∂V ds ∂I D
举重比赛规则Saturation Region
Condition V ov≥0and V ds≥V dsat
I D becomes purely a function of the gate voltage,V ov (not of V ds)
I D=1
2
µC ox
W
L
V2
ov
Figure7:A saturation-centric view of transistor bi-
asing.
Saturation is the desired operating region for most of
the transistors in the signal path,other than switches.
In fact,for the rest of this article,we will oper-
ate almost exclusively in the saturation region.As
long as each transistor has enough headroom,mean-
ing that we maintain V ds≥V dsat,then we can adopt
a saturation-centric point of view,which is shown in
Fig.7.Note that,as V ov increas,not only does I D
increa,but g m grows as well due to the quadratic
equation.In other words,g m is a function of V ov.
Keep this picture in the back of your mind.
0.4.2Introduction to the V ov-Bad
Design Methodology
g m,f T and Making Sen of Transistor-Level
一体式电脑
Design
朝鲜是什么国家Now that we have been introduced to V ov,we can de-
velop it into a design variable.Remember,we even-
tually need it to tie into the small signal model shown
in Fig.2.Thefirst element in the model we will work
on is g m,which is just the slope of the I D vs.V ov
curve.
g m=
∂I D
∂V ov
=µC ox
W
L
V ov
With a little algebraic manipulation,we can derive
an interesting equation,which,as you may recognize,
contains both of the biasing variables that we are
investigating.
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