【DC】DC的TCL脚本常⽤命令
0 clock命令：Tcl Built-In Commands
clock conds：
Return the current date and time as a system-dependent
integer value. The unit of the value is conds, allowing it to be ud for relative time calculations.
1. file命令：Tcl Built-In Commands
file option name ?arg arg ...?
file exists name：
Returns 1 if file name exists and the current ur has
arch privileges for the directories leading to it, 0 otherwi.
1. exec函数族的作⽤是根据指定的⽂件名找到可执⾏⽂件，并⽤它来取代调⽤进程的内容，换句话说，就是在调⽤进程内部执⾏⼀个可执⾏⽂件。
mkdir ⽬录名：创建⽬录
1. define_design_lib命令：
结构：define_design_lib library_name -path directory
The define_design_lib command maps a design library to a UNIX direc-tory. The directory is ud to store intermediate reprentations of designs.
1. sh 是 shell 的简称，在执⾏脚本的时候是⽤sh + 脚本名的⽅式来执⾏；
sh rm -rf ./output/* 其中，rm 是⽂件⽬录删除命令，-f 直接删除，-r 全部删除，*匹配任意长的字符。
1. alib_library_analysis_path：
Specifies a single path, similar to a arch path, for reading and writing the alib files that correspond to the target libraries.This variable specifies the path from which the tool loads alibs during compile
2. source命令:Read a file and evaluate it as a Tcl script.
结构：source [-echo] [-verbo] [-continue_on_error] file
-echo Echoes each command as it is executed. Note that this option is
a non-standard extension to Tcl.
-verbo
Displays the result of each command executed. Note that error
messages are displayed regardless. Also note that this option
is a non-standard extension to Tcl.
1. Default: target_library = "your_library.db"
link_library = "* your_library.db"
target_library: Specifies the list of technology libraries of components to be ud when compiling a design.
link_library : Specifies the list of design files and libraries ud during linking.
2. suppress_message命令：suppress_message [message_list]
Disables printing of one or more informational or warning messages.
1. suppress_errors命令：
Specifies a list of error codes for which messages are to be suppresd during the current shell ssion.
1. symbol_library：Specifies the symbol libraries to u during schematic generation
1. verbo_messages：Caus more explicit system messages to be displayed during the current ssion.
2. auto_link_options :This variable specifies the link command options to be ud when link is invoked automatically. The default value is -all.
3. verilogout_no_tri :Declares three-state nets as Verilog "wire" instead of "tri." This variable is uful in eliminating "assign" primitives and "tran" gates in the
Verilog output.
4. dc_shell_status :Contains the return value of the previously executed command.Therefore the variable can be of anytype.Most commands return the
integer 0 to indicate failure or 1 to indicate successful execution. This variable is most often ud as the conditional expression of an i f or while command.
5. sh_new_variable_message:The sh_new_variable_message variable controls a debugging feature for tracing the creation of new variables.Its
primary debugging purpo is to catch the misspelling of an application-owned global variable. When t to true, an informational message (CMD-041) is displayed when a variable is defined for the first time at the command line. When t to fal, no message is displayed.
6. compile_qmap_propagate_constants : Controls whether the compile command tries toi dentify and remove constant registers and propagate the constant
value throughout the design. When the value is true (the default), compile tries to identify and remove constant quential elements in the design, which improves the area of the design.
美国节假日7. compile_delete_unloaded_quential_cells :
Controls whether the compile command deletes unloaded quential cells. By default, the compile command deletes unloaded quential cells. To retain such cells, t the compile_delete_unloaded_quential_cells variable to fal.
8. compile_prerve_subdesign_interfaces :
Controls whether the compile command prerves the subdesign interface. When this variable is t to true, it disables customization of logic external to a subdesign during compile, and prerves the subdesign interface. When t to fal (the default), compile customizes the logic external to a subdesign bad on the subdesign's internal logic.
1. hdlin_prerve_quential :
Controls whetherthe elaborate and read commands retain unloaded quential cells in the design.
1. hdlin_enable_rtldrc_info :
When true, RTL TestDRC filename and linenumber information is created for designs procesd by subquent dc_shell
commands.When fal, no RTL TestDRC information is created.
1. echo命令：显⽰输出
1. dont_u命令：
Disables the specified library cells so that they are not added to a design during compile. Set with t_dont_u.
1. alias命令：为⼀个可执⾏程序定义别名
1. "dc_shell-f l | tee dc.log"
dc_shell -f ⽂件名表明启动dc_shell后⾃动执⾏可执⾏⽂件；
"|"是管道机制符号，命令1 |命令2|…|命令n 管道机制是前⼀个命令的输出作为后⼀个命令的输⼊；
tee命令：tee [-ai] filename 读取标准输⼊的数据，并将其内容输出到指定⽂件，默认为覆盖⽅式，-a 表⽰追加⽅式
晴川历历
1. report_timing命令：Displays timing information about a design。
report_timing [options] :
[options]举例如下：
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[-sig 数字] =>[ -significant_digits digits] Specifies the number of digits to the right of the decimal point to report. Allowed values are from 0
through 13. The default is 2.
[-cap] =>[-capacitance] Indicates that total (lump) capacitance be shown in the path report.
[-tran]=>[-transition_time]Shows the net transition time for each driving pin in the path report.
[-nets] Shows nets in the path report.The default is not to show nets.To show the delay for the nets, u the -input_pins option.
[-input_pins] Shows input pins in the path report. The default is to show only output pins. This option also shows the delays of the nets
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connected to the pins.
[-to to_list]Reports only the paths to the named pins, ports, or clocks.
[-from from_list] Reports only the paths from the named pins, ports, or clocks
1. t_svf 命令：t_svf filename [-append][-off]
Generates a Formality tup information file for efficient compare point matching in Formality
This command caus Design Compiler to start recording tup information for Formality, the Synopsys formal verification tool. The SVF ("Setup Verification for Formality") file that is produced is ud by Formality during the matching step to facilitate the alignment of compare points.
1. analyze 命令：analyze [options] file_list
Analyzes the specified HDL source files; stores the design templates they define into the specified library in a format ready to elaborate and specialize as needed to link a full design.
复方甘草片副作用Some options:
[-format verilog | sverilog | vhdl] : Specifies the format of the files that are to be analyzed. The supported formats are Verilog,
SystemVerilog, and VHDL.
1. elaborate命令：elaborate design_name [options]
Builds a design from the intermediate format of a Verilog module, a VHDL entity and architecture, or a VHDL configuration.
-Reads the intermediate files；-builds the 'GTECH' design in DC memory (unmapped ddc format)；-Sets the current design to the specified design；- Links and auto-loads the specified design；
- Allows specification of parameter values:
1. current_design命令（before link）: ts the working design
current_design [design]The current_design command ts the working design for many commands. If you do not specify any
arguments, the current_design command returns the name of the current working design.
30 link命令：Resolves design references. 语法结构：link，没有参数；
Performs a name-bad resolution of design references for the current design.
For a design to be complete, it needs to be connected to all of the library components and designs it references. The references must be located and linked to the current design in order for the design to be functional. The purpo of this command is to locate all of the designs and library components referenced in the current design and connect (link) them to the current design.
31 uniquify_naming_style：Specifies the naming convention to be ud by the uniquify command. The variable string must
contain only one %s (percent s) and one %d (percent d) character quence. To u a percent sign in the design name, two are needed
in the string (%%).
32 uniquify命令：uniquify [-force]|[other options]
Removes multiply-instantiated hierarchy in the current design by creating a unique design for each cell instance.If a new design is generated, it is copied from the original design, and placed in the same file as the current design. The new design is named according to the uniquify_naming_style variable.
[-force]Indicates that instances are to be renamed even if they are already unique or are assigned the dont_touch attribute. The top-level design is not
renamed.
33 write是write_file 的别名：Writes a design netlist or schematic from memory to a file.
结构：write_file [-format output_format] [-hierarchy] [-no_implicit] [-output output_file_name][-scenarios scenario_list][-library library_name] [-include_anchor_cells] [design_list]
[-format output_format]: Specifies the output format of the design. the default format is ddc;other format ：verilog，svsim, vhdl [-hierarchy]: Writes out all the designs in the hierarchy, starting from the designs specified in design_list.
[-output output_file_name]:Specifies a single file into which designs are to be written.By default,the command writes each design into a parate file
nameddesign.suffix, .ddc –ddc;.v –verilog ; .sv –svsim;.vhd -vhdl
34 remove_sdc命令：Removes all Synopsys Design Constraints (SDC).
35 remove_clock命令：remove_clock clock_list | -all
Removes clocks from the current design
36 ret_design命令，没有参数：Removes all ur-specified objects and attributes from the current design, except tho defined by using
the t_attributecommand.
37 create_clock命令：Creates a clock object and defines its waveform in the current design.
语法：create_clock [-name clock_name] [-add] [source_objects] [-period period_value] [-waveform edge_list] [-
comment comment_string]
[-name clock_name]：Specifies the name of the clock being created.
[-period period_value]: Specifies the period of the clock waveform in library time units
[-waveform edge_list]: Specifies the ri and fall edge times, in library time units, of the clock over an
entire clock period.
[source_objects]: Specifies a list of pins or ports on which to apply this clock.
38 get_pins命令：Creates a collection of pins that match the specified criteria。
get_ports 命令：Creates a collection of ports from the current design that match the specified criteria.
all_inputs 命令：Returns a collection of input or inout ports in the current design.单眼皮的优点
all_outputs命令：Returns a collection of output or inout ports in the current design.
39 get_clocks命令：Creates a collection of clocks from the current design.
get_designs：Creates a collection of one or more designs loaded into the tool.
get_nets : Creates a collection of nets that match the specified criteria.
40 t_clock_latency命令：Specifies clock network latency.
t_clock_latency [-ri] [-fall] [-min] [-max] [-source] [-early] [-late] [-clock clock_list] delay object_list
[delay]: Specifies the clock latency value.
字开头的成语[object_list] :Specifies the clocks, ports, and pins for which the clock latency is to be t.
41 t_clock_uncertainty命令：Specifies the uncertainty (skew) of the specified clock networks.
t_clock_uncertainty [object_list | -from from_clock | -ri_from ri_from_clock | -fall_from fall_from_clock -to to_clock | -ri_to ri_to_clock | -fall_tofall_to_clock] [-ri] [-fall] [-tup] [-hold] uncertainty
[-tup ]:Indicates that the uncertainty applies only to tup checks. By default, the uncertainty applies to both tup and hold checks.
42 t_input_delay命令：Sets input delay on pins or input ports relative to a clock signal.
t_input_delay delay_value [-reference_pin pin_port_name] [-clock clock_name] [-clock_fall] [-level_nsitive] [-
network_latency_included] [-source_latency_included] [-ri] [-fall] [-max] [-min] [-add_delay] port_pin_list
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43 remove_from_collection命令：Removes objects from a collection, resulting in a new collection. The ba collection
remains unchanged.
44 t_output_delay命令：Sets output delay on pins or output ports relative to a clock signal。
t_output_delay delay_value [-reference_pin pin_port_name] [-clock clock_name [-clock_fall] [-level_nsitive]] [-
network_latency_included] [-source_latency_included] [-ri] [-fall] [-max] [-min] [-add_delay] [-group_path group_name] port_pin_list
45 t_input_transition命令：Sets the max_transition_ri, max_transition_fall, min_transition_ri, or min_transition_fall attributes to the specified
transition values on the specified input and inout ports.
t_input_transition transition [-ri] [-fall][-min][-max] port_list
