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I 2C Interface to 8051 Microcontroller
Application Staff
Introduction to I 2C
The I 2C (Inter-Integrated Circuit) bus is a 2-wire rial bus which provides a small networking system for cir-cuits sharing a common bus. The devices on the bus can vary from microcontrollers to LCD drivers to E 2PROMs.Two bi-directional lines, a rial data (SDA) and a rial clock (SCL) line, transmit data between the devices connected to the bus. Each device has a unique address to differentiate it from the other devices on the bus, and each is configured either as a master or a slave when performing data transfers (e Table 1). A master is the device which initiates a data transfer and gener-ates the clock signals necessary for the transfer. Any device that is addresd is considered a slave. The I 2C bus is a multi-master bus, which means that more than one device that is capable of controlling the bus can be connected to it.
Each transmission on the bus begins with the Master nding a Start condition and ends with a Stop condition (e Figure 1). The Master then nds the address of the particular slave device it is requesting. The first four bits of this slave address are fixed as 1010. The next three bits specify a combination of the device address bit(s)and which 2K array of the memory is being addresd (e Figure 2). The last bit of the slave address specifies whether a read or write operation is to be performed.When this bit is a “1”, a read operation is performed, and when it is a “0”, a write operation is performed.
Table 1. Definition of I 2C Bus Terminology
Term Description
Transmitter The device which nds the data to the bus.Receiver The device which receives the data from the bus.
Master The device which initiates a transfer, generates clock signals and terminates a transfer.Slave The device addresd by a master.
Multi-Master More than one master can attempt to control the bus at the same time without corrupting the message.
Arbitration Procedure to ensure that, if more than one master simultaneously tries to control the bus,only one is allowed to do so, and the message is not corrupted.Synchronization
Procedure to synchronize the clock signals of two or more devices.
Figure 1. START/STOP Timing
START BIT
SDA
STOP BIT
SCL
5194 FHD F01
5194 FHD F07
Figure 2. Slave Address Bits
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1
A2地基工程
A1
A0
R/W
© 2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
APPLICATION NOTE AN2
Document No. 6001, Rev. A
I 2C Interface to 8051 Microcontroller
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Document No. 6001, Rev. A
After the Master nds a Start condition, the slave (E 2PROM) monitors the bus and responds with an acknowledge when its address matches the transmitted slave address (e Figure 3). The device then performs a read or write operation depending on the state of the CAT24CXX Interface to 8051 Microcontroller Catalyst’s I 2C family of devices interfaces directly with industry standard microcontrollers such as the Intel MCS-51 family. This family includes 8031/8051 and 8032/8052 (ROMless/ROM) family types.
Catalyst I 2C E 2PROMs are 2-wire interface, nonvolatile memories ranging from 2K bits (CAT24WC
02) to 64K bits (CAT24WC64) in density. They adhere to the I 2C protocol which us 2 lines, a data (SDA) and rial clock (SCL) line for all transmissions, as described above.
The CAT24WC02 E 2PROM has an 8 byte page write buffer and a write protect pin for inadvertent write protec-tion. The CAT24WC04, CAT24WC08 and CAT24WC16devices have 16 byte page write buffers. Up to eight CAT24WC02 devices, four CAT24WC04 devices, two CAT24WC08 devices and one CAT24WC16 device may be connected to an I 2C bus and addresd inde-pendently. The CAT24WC32/64 has a 32-byte Page Write buffer and up to eight devices may be connected to an I 2C bus and addresd independently. Unique addressing is accomplished through hard-wiring ad-dress pins A0, A1 and A2 on each device. An example program follows that demonstrates simple byte write and byte read routines as well as page mode and quential read routines using an 8051 microcontroller.Figure 4 shows a simple hardware interface.
Figure 3. ACKNOWLEDGE Timing
5194 FHD F02
ACKNOWLEDGE
START
SCL FROM MASTER
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER
I2C Interface to 8051 Microcontroller Figure 4. I2C Interface to 8051 Microcontroller
3Document No. 6001, Rev. A
I 2C Interface to 8051 Microcontroller
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Document No. 6001, Rev. A梦见狗打架
<< ASM51 >> CROSS ASSEMBLER VER.2.5M ASSEMBLE LIST DATE: PAGE: 1 LOC. OBJECT LINE STATEMENT I2C_8051.ASM
1
;**********************************************************************
2 ; THE FOLLOWING CODE SHOWS AN INTERFACE BETWEEN AN 8051
MICROCONTROLLER
3 ; AND CATALYST’S I2C FAMILY OF EEPROMS.
4 ;
5 ; IT DEMONSTRATES A BYTE WRITE/BYTE READ ROUTINE AND A PAGE MODE
6 ; WRITE/SEQUENTIAL READ ROUTINE. IT USES TWO LINES FROM PORT 1
7 ; (P1.0 AND P1.1) OF THE 8051 TO COMMUNICATE WITH THE CAT24CXX.
8 ;
9 ; THIS PROGRAM WILL WORK WITH THE CAT24WC02/04/08/16 DEVICES.
NOTE:
10 ; THE 24WC02 HAS AN 8 BYTE PAGE BUFFER AND 24WC04/08/16 HAVE A 11 ; 16-BYTE PAGE
BUFFER.;*********************************************************************
12
0090 13 SCL BIT P1.0 ;SCL BIT IS PORT 1,BIT 0 0091 14 SDA BIT P1.1 ;SDA BIT IS PORT 1,BIT 1 0005 15 SLV_ADDR EQU 0101B ;F
IXED SLAVE ADDRESS BITS REG 16 DATAOUT EQU R5 ;DATA READ FROM DEVICE 0085 17 ACK_READ EQU 10000101B ;READ FOR ACK POLLING
18
—— 19 DSEG 0030 20 ORG 0030H
21
0030 22 PAGE_DATA: DS 1 0031 23 BLK_ADDR: DS 1 0032 24 BYTE_ADDR: DS 1 0033 25 BYTE_DATA: DS 1
26
0040 27 ORG 40H 0040 28 STACK: DS 31
29
—— 30 CSEG 0040 31 ORG 0040H 0040 02 01 00 32 LJMP BEGIN
33
0100 34 ORG 0100H 0100 75 81 40 35 BEGIN: MOV SP,#STACK ;INITIALIZE STACK POINTER
36
0103 75 31 00 37 MOV BLK_ADDR,#000B ;INITIALIZE 2K BLOCK
0106 75 33 55 38 MOV BYTE_DATA,#55H ;BYTE DATA 0109 75 32 00 39 MOV BYTE_ADDR,#00H ;BYTE ADDRESS 010C 75 30 AA 40 MOV PAGE_DATA,#0AAH ;PAGE DATA
41
010F 31 45 [0145] 42 ACALL PAGE_WR ;CALL PAGE WRITE ROUTINE
0111 51 1D [021D] 43 ACALL SEQ_RD ;CALL SEQ. READ ROUTINE
0113 31 1A [011A] 44 ACALL BYTE_WR ;CALL BYTE WRITE ROUTINE
泡妹0115 31 D6 [01D6] 45 ACALL SELECT_RD ;CALL BYTE READ
I2C Interface to 8051 Microcontroller ROUTINE
0117 02 01 17 46 DONE: LJMP DONE ;LOOP UNTIL RESET OCCURS
47
48 ;*******************************************
49
50 ;************** BYTE WRITE *****************
51
011A 31 95 [0195] 52 BYTE_WR: ACALL START_BIT ;SEND START BIT
011C 74 05 53 MOV A,#SLV_ADDR ;FIRST 4 SLAVE AD-DRESS
011E 7F 04 54 MOV R7,#4H ;BITS
0120 31 89 [0189] 55 ACALL SHFTO
赛睿耳机0122 E5 31 56 MOV A,BLK_ADDR ;2K BLOCK ADDRESS
0124 7F 03 57 MOV R7,#3H
0126 31 89 [0189] 58 ACALL SHFTO
<< ASM51 >> CROSS ASSEMBLER VER.2.5M ASSEMBLE LIST DATE: PAGE: 2慈悲串经
LOC. OBJECT LINE STATEMENT I2C_8051.ASM
0128 74 00 59 MOV A,#00H ;R/W BIT SET TO 0 FOR 012A 7F 01 60 MOV R7,#1H ;WRITE
012C 31 89 [0189] 61 ACALL SHFTO
012E 31 AA [01AA] 62 ACALL SLAVE_ACK
63
0130 E5 32 64 MOV A,BYTE_ADDR ;BYTE ADDRESS
0132 7F 08 65 MOV R7,#8H
0134 31 89 [0189] 66 ACALL SHFTO
0136 31 AA [01AA] 67 ACALL SLAVE_ACK
0138 E5 33 68 MOV A,BYTE_DATA ;BYTE DATA
013A 7F 08 69 MOV R7,#8H
013C 31 89 [0189] 70 ACALL SHFTO
013E 31 AA [01AA] 71 ACALL SLAVE_ACK
0140 31 A1 [01A1] 72 ACALL STOP_BIT ;STOP BIT
0142 31 74 [0174] 73 ACALL ACK_POL ;CALL ACK POLLING, WAIT
0144 22 74 RET ;FOR END OF WRITE CYCLE
75 ;*******************************************
76
77 ;************** PAGE WRITE *****************
78
0145 31 95 [0195] 79 PAGE_WR: ACALL START_BIT ;SEND START BIT
0147 74 05 80 MOV A,#SLV_ADDR ;FIRST 4 SLAVE AD-DRESS
0149 7F 04 81 MOV R7,#4H ;BITS
014B 31 89 [0189] 82 ACALL SHFTO
014D E5 31 83 MOV A,BLK_ADDR ;2K BLOCK ADDRESS
014F 7F 03 84 MOV R7,#3H
0151 31 89 [0189] 85 ACALL SHFTO
0153 74 00 86 MOV A,#00H ;R/W BIT SET TO 0 FOR 0155 7F 01 87 MOV R7,#1H ;WRITE
0157 31 89 [0189] 88 ACALL SHFTO
0159 31 AA [01AA] 89 ACALL SLAVE_ACK
015B E5 32 90 MOV A,BYTE_ADDR ;BYTE ADDRESS
015D 7F 08 91 MOV R7,#8H
015F 31 89 [0189] 92 ACALL SHFTO
0161 31 AA [01AA] 93 ACALL SLAVE_ACK
蜂蛰伤0163 7C 0F 94 MOV R4,#0FH
95 NEXT_DATA: ;WRITE 16 BYTES TO
0165 E5 30 96 MOV A,PAGE_DATA ;EEPROM
0167 7F 08 97 MOV R7,#8H
5Document No. 6001, Rev. A
I 2C Interface to 8051 Microcontroller
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Document No. 6001, Rev. A
0169 31 89 [0189] 98 ACALL SHFTO
016B 31 AA [01AA] 99 ACALL SLAVE_ACK 016D DC F6 [0165] 100 DJNZ R4,NEXT_DATA 016F 31 A1 [01A1] 101 ACALL STOP_BIT
0171 31 74 [0174] 102 ACALL ACK_POL ;CALL ACK
POLLING,WAIT 0173 22 103 RET ;FOR END OF WRITE
CYCLE
104 ;******************************************* 105
106 ;************** ACK_POL ******************** 107
槐花开了
0174 7B 40 108 ACK_POL: MOV R3,#40H ;# OF TIMES TO POLL 0176 DB 02 [017A] 109 ACK_LOOP: DJNZ R3,DONE_YET ;DEVICE 0178 80 0C [0186] 110 SJMP DN_ACKPOL
017A 31 95 [0195] 111 DONE_YET: ACALL START_BIT ;SEND START BIT 017C 74 85 112 MOV A,#ACK_READ ;SEND READ 017E 7F 08 113 MOV R7,#8H 0180 31 89 [0189] 114 ACALL SHFTO
0182 31 AA [01AA] 115 ACALL SLAVE_ACK ;SEND ACKNOWLEDGE
0184 40 F0 [0176] 116 JC ACK_LOOP ;LOOP IF NO ACK RCVD,<< ASM51 >> CROSS ASSEMBLER VER.2.5M ASSEMBLE LIST DATE: PAGE: 3 LOC. OBJECT LINE STATEMENT I2C_8051.ASM
117 ;JUMP IF ACK RCVD 0186 31 A1 [01A1] 118 DN_ACKPOL: ACALL STOP_BIT ;SEND STOP BEFORE RETURN 0188 22
119 RET
120 ;******************************************* 121
122 ;************** SHFTO ********************** 123
0189 C2 90 124 SHFTO: CLR SCL 018B C2 90 125 NXTSHF: CLR SCL
018D 13 126 RRC A ;ROTATE DATA INTO CARRY
018E 92 91 127 MOV SDA,C ;SEND CARRY TO SDA 0190 D2 90
128 SETB SCL
0192 DF F7 [018B] 129 DJNZ R7,NXTSHF 0194 22
130 RET
131 ;******************************************* 132
133 ;************** START BIT ****************** 134
0195 D2 90 135 START_BIT: SETB SCL ;START BIT 0197 00 136 NOP
0198 D2 91 137 SETB SDA 019A 00 138 NOP
019B C2 91 139 CLR SDA 019D 00 140 NOP
019E C2 90 141 CLR SCL 01A0 22
142 RET
143 ;******************************************* 144
芹菜叶能吃吗145 ;************** STOP BIT ******************* 146
01A1 C2 91
147 STOP_BIT: CLR SDA ;STOP BIT
