Chapter 5:DSP Blocks in Stratix III Devices
Operational Mode Descriptions
A single DSP block can implement up to two independent 44-bit accumulators.
发生火灾后如何逃生The dynamic accum_sload control signal is ud to clear the accumulation. A
logic1 value on the accum_sload signal synchronously loads the accumulator
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with the multiplier result only, while a logic0 enables accumulation by adding or
subtracting the output of the DSP block (accumulator feedback) to the output of the
multiplier and first-stage adder.
1The control signal for the accumulator and subtractor is static and therefore has to be configured at compile time.
This mode supports the round and saturation logic unit as it is configured as an 18-bit
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multiplier accumulator. You can u the pipeline registers and output registers within
the DSP block to increa the performance of the DSP block.
Shift Modes
Stratix III devices support the following shift modes for 32-bit input only:
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■Arithmetic shift left, ASL[N]
■Arithmetic shift right, ASR[32-N]
■Logical shift left, LSL[N]
■Logical shift right, LSR[32-N]
■32-bit rotator or Barrel shifter, ROT[N]
1You can switch the shift mode between the modes using the dynamic rotate and shift control signals.
The shift mode in a Stratix III device can be easily ud by the soft embedded
processor such as Nios®II to perform the dynamic shift and rotate operation.
Figure5–20 shows the shift mode configuration.
The shift mode makes u of the available multipliers to logically or arithmetically
shift left, right, or rotate the desired 32-bit data. The DSP block is configured like the旅游知道
independent 36-bit multiplier mode to perform the shift mode operations.
幼师论文The arithmetic shift right requires signed input vector. During arithmetic shift right,
the sign is extended to fill the MSB of the 32-bit vector. The logical shift right us
unsigned input vector. During logical shift right, zeros are padded in the most
significant bits shifting the 32-bit vector to the right. The barrel shifter us unsigned
input vector and implements a rotation function on a 32-bit word length.
Two control signals rotate and shift_right together with the signa and signb
signals, determining the shifting operation. Examples of shift operations are listed in
Table 5–5 on page5–31.
Chapter 5:DSP Blocks in Stratix III Devices
Chapter Revision History
Chapter Revision History
Table 5–10 lists the revision history for this chapter.
Table 5–10. Document Revision History
Chapter 6:Clock Networks and PLLs in Stratix III Devices
Clock Networks in Stratix III Devices
Table6–6 lists the connectivity between the dedicated clock input pins and RCLKs in
device Quadrant 4. A given clock input pin can drive two adjacent regional clock出差补贴
networks to create a dual-regional clock network.
Table6–6.Clock Input Pin Connectivity to Regional Clock Networks (Quadrant 4)
Table6–7 lists the dedicated clock input pin connectivity to Stratix III device PLLs. Table6–7.Stratix III Device PLLs and PLL Clock Pin Drivers (Part 1 of 2) (Note1)
Chapter 6:Clock Networks and PLLs in Stratix III Devices
Chapter Revision History
II–2Section II: I/O Interfaces
Revision History
