Low Power 250 MSPS 10-Bit DAC 1.8 V
CMOS Direct Digital Synthesizer
AD9913
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its u, nor for any infringements of patents or other rights of third parties that may result from its u. Specifications subject to change without notice. No licen is granted by implication or otherwi under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners.
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FEATURES
50 mW at up to 250 MSPS internal clock speed 100 MHz analog output Integrated 10-bit DAC
0.058 Hz or better frequency resolution 0.022° pha tuning resolution
Programmable modulus in frequency equation单反机
Pha noi ≤ –135 dBc per Hz @ 1 kHz offt (DAC output) (<115 dBc per Hz when using on-board PLL multiplier) Excellent dynamic performance
>80 dB SFDR @ 100 MHz (±100 kHz offt) A OUT Automatic linear frequency sweeping capability 8 frequency or pha offt profiles 1.8 V power supply
Software and hardware controlled power-down Parallel and rial programming options 32-lead LFCSP package
Optional PLL REF_CLK multiplier
谓语动词有哪些Internal oscillator (can be driven by a single crystal) Pha modulation capability
APPLICATIONS
Portable and handheld equipment Agile LO frequency synthesis Programmable clock generator
新加坡菜
FM chirp source for radar and scanning systems
GENERAL DESCRIPTION
The AD9913 is a complete direct digital synthesizer (DDS) designed to meet the stringent power consumption limits of portable, handheld, and battery-powered equipment. The AD9913 features a 10-bit digital-to-analog converter (DAC) operating up to 250 MSPS. The AD9913 us advanced DDS technology, coupled with an internal high speed, high performance DAC to form a complete, digitally-program-mable, high frequency synthesizer capable of generating a frequency agile analog output sinusoidal waveform at up to 100 MHz.
The AD9913 provides fast frequency hopping and fine tuning resolution. The AD9913 also offers fine resolution pha offt control. Control words are loaded into the AD9913 through the rial or parallel I/O port. The AD9913 also supports a ur-defined linear sweep mode of operation for generating highly linearized swept waveforms of frequency. To support various methods of generating a system clock, the AD9913 includes an oscillator, allowing a simple crystal to be ud as the frequency reference, as well as a high speed clock multiplier to convert the reference clock frequency up to the full system clock rate. For power saving considerations, many of the individual blocks of the AD9913 can be powered down when not in u.
The AD9913 operates over the extended industrial temperature range of −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
07002-001
Figure 1.
AD9913
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TABLE OF CONTENTS
五毛钱的愿望
1 1 Functional 1 .3 3 Absolute 5 5 5 Pin Configuration and 6 Typical 8 11 Theory 12 12 13
..........................13 I/13 .13 Modes 14 Single 14 Direct 14 Programmable 14 Linear 14 Clock Input (REF_CLK)................................................................18 21 I/22 22 Parallel I/23 Register Map and 25 .25 Register 27 31 Ordering Guide.. (31)
REVISION HISTORY
10/07—Revision 0: Initial Version
AD9913
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SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
AVDD (1.8 V), DVDD (1.8 V), and DVDD_I/O = 1.8 V ± 5%, T = 25°C, R SET = 4.64 kΩ, DAC full-scale current = 2 mA, external reference clock frequency = 250 MHz with REF_CLK multiplier disabled, unless otherwi noted. Table 1.
Parameter Conditions/Comments Min Typ Max Unit REF_CLK INPUT CHARACTERISTICS Frequency Range REF_CLK Multiplier Disabled 250 MHz Enabled 250 MHz REF_CLK Input Divider Frequency Full temperature range 83 MHz VCO Oscillation Frequency VCO1 16 250 MHz VCO2 100 250 MHz PLL Lock Time 25 MHz reference clock, 10× PLL 60 μs External Crystal Mode 25 MHz CMOS Mode VIH 0.9 V VIL 0.65 V Input Capacitance 3 pF Input Impedance (Differential) 2.7 kΩ Input Impedance (Single-Ended) 1.35 kΩ Duty Cycle 45 55 % REF_CL
K Input Level 355 1000 mV p-p DAC OUTPUT CHARACTERISTICS Full-Scale Output Current 4.6 mA Gain Error −14 −6 %FS Output Offt +0.1 μA Differential Nonlinearity −0.4 +0.4 LSB Integral Nonlinearity −0.5 +0.5 LSB AC Voltage Compliance Range ±400 mV SPURIOUS-FREE DYNAMIC RANGE Refer to Figure 6 SERIAL PORT TIMING CHARACTERISTICS SCLK Frequency 32 MHz SCLK Pul Width Low 17.5 ns High 3.5 ns SCLK Ri/Fall Time 2 ns Data Setup Time to SCLK 5.5 ns Data Hold Time to SCLK 0 ns Data Valid Time in Read Mode 22 ns PARALLEL PORT TIMING CHARACTERISTICS PCLK Frequency 33 MHz PCLK Pul Width Low 10 ns High 20 ns PCLK Ri/Fall Time 2 ns Address/Data Setup Time to PCLK 3.0 ns Address/Data Hold Time to PCLK 0.3 ns Data Valid Time in Read Mode 8 ns IO_UPDATE/PROFILE(2:0) TIMING Setup Time to SYNC_CLK 0.5 ns Hold Time to SYNC_CLK 1 SYNC_CLK cycles
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Parameter Conditions/Comments Min Typ Max Unit MISCELLANEOUS TIMING CHARACTERISTICS Wake-Up Time 1 Fast Recovery Mode 1 SYSCLK cycles 2Full Sleep
Mode 60 μs Ret Pul Width High 5 SYSCLK cycles DATA LATENCY (PIPELINE DELAY) Frequency, Pha-to-DAC Output Matched latency enabled 11 SYSCLK cycles Frequency-to-DAC Output Matched latency disabled 11 SYSCLK cycles Pha-to-DAC Output Matched latency disabled 10 SYSCLK cycles Delta Tuning Word-to-DAC Output (Linear Sweep) 14 SYSCLK cycles CMOS LOGIC INPUTS Logic 1 Voltage 1.2 V Logic 0 Voltage 0.4 V Logic 1 Current −700 +700 nA Logic 0 Current −700 +700 nA Input Capacitance 3 pF CMOS LOGIC OUTPUTS 1 mA load Logic 1 Voltage 1.5 V Logic 0 Voltage 0.125 V POWER SUPPLY CURRENT DVDD (1.8 V) Pin Current Consumption 46.5 mA DAC_CLK_AVDD (1.8 V) 4.7 mA DAC_AVDD (1.8 V) Pin Current Consumption 6.2 mA PLL_AVDD (1.8 V) 1.8 mA CLK_AVDD (1.8 V) Pin Current Consumption 4.3 mA POWER CONSUMPTION Single Tone Mode PLL enabled, CMOS input 50 66.5 mW PLL disabled, differential input 57 70.5 mW PLL enabled, XTAL input 52 68.5 mW Modulus Mode PLL disabled 94.6 mW Linear Sweep Mode PLL disabled 98.4 mW Power-Down
ull 15 mW Safe PLL enabled 44.8 mW PLL Modes VCO 1 Differential Input Mode 11 mW CMOS Input Mode 7.5 mW Crystal Mode 5.4 mW VCO 2 Differential Input Mode 15 mW CMOS Input Mode 11.5 mW Crystal Mode 9.4 mW
1 Refer to the Power-Down Features ction.
2
SYSCLK cycle refers to the actual clock frequency ud on-chip by the DDS. If the reference clock multiplier is ud to multiply the external reference clock frequency, the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier and divider are not ud, the SYSCLK frequency is the same as the external reference clock frequency.
AD9913
遗传病
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ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating Maximum Junction Temperature 150°C AVDD, DVDD 2 V Digital Output Current 5 mA Storage Temperature –65°C to +150°C Operating Temperature –40°C to +105°C Lead Temperature (Soldering, 10 c) 300°C θJA 36.1°C/W θJC 4.2°C/W
Stress above tho listed under Absolute Maximum Ratings may cau permanent damage to the device. This is a stress
rating only and functional operation of the device at the or any other conditions above tho indicated in the operational ction of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION
EQUIVALENT CIRCUITS
DIGITAL INPUTS
DAC OUTPUTS
AVOID OVERDRIVING DIGITAL INPUTS.
FORWARD BIASING ESD DIODES MAY COUPLE DIGITAL NOISE ONTO POWER PINS.
MUST TERMINATE OUTPUTS TO AGND FOR CURRENT FLOW. DO NOT EXCEED THE OUTPUT VOLTAGE COMPLIANCE RATING.
07002-002
Figure 2. Equivalent Input and Output Circuits
AD9913
山村教师
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胰腺炎的早期症状PIN CONFIGURATION AND FUNCTION DESCRIPTIONS督导检查工作简报
1PS2/ADR5/D52PS1/ADR4/D43PS0/ADR3/D3
4DVDD 5DGND 6ADR2/D27ADR1/D18
ADR0/D0K )D )
E _C T L E S E T 07002-003
Figure 3. Pin Configuration
