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骚扰电话拦截利用Quartus II进行设计的练习手册
摘要：本文介绍了如何利用Quartus II进行设计的七个练习：第一个，利用MegaWizard插件管理器创建一个乘法器，检测所有的连接是否正确；第二个，利用现有的文件创建一个库，分析不同的时序参数，利用DSP模块实现乘法器，为I/O引脚赋值并实现I/O分析；第三个，分析设计的时序；第四个，对时钟引脚设置多个周期，说明Slack时刻表；第五个，新建一个向量波形文件，运行功能仿真；第六个和第七个，利用可编程的JTAG链新建一个链式文件，采用程序规划工具配置器件。
关键词：Quartus II，插件管理器，功能仿真，可编程逻辑
Exerci Manual
for
Designing with Quartus II
Exercis Designing with Quartus II
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Copyright © 2004 Altera Corporation
A-MNL-QUARTUSII-EX-09 v4.0
Designing with Quartus II
Exercis
世界杯赛Copyright © 2004 Altera Corporation A-MNL-QUARTUSII-EX-09v4.0会字开头的成语
3 Exerci 1
Exercis Designing with Quartus II Copyright © 2004 Altera Corporation
A-MNL-QUARTUSII-EX-09 v4.0
43月4日是什么星座
Exerci 1 Objectives:
• U the MegaWizard Plug-in Manager and create a multiplier
• Inrt wires and pins into design
• Verify that all connections are made correctly.
Pipelined Multiplier Design
Figure 1
Designing with Quartus II Exercis
Copyright © 2004 Altera Corporation
A-MNL-QUARTUSII-EX-09v4.0 5
Step 1 (Open the project and create schematic file)
In this exerci, you will u a project which has been created for you. This exerci focus on the schematic design capabilities in Quartus ® II.
1. If it is not already started, launch the Quartus II software using the start menu or
desktop icon if one exists on your machine.
2. Select File ⇒ Open project… Brow to <Quartus II\Lab install
directory>\QII4_0\Lab1\. Select the project pipemult.qpf and click on Open .
3. Select File ⇒ New and lect Block Diagram/Schematic File
4. Select File ⇒ Save As and save the file as
<Quartus II\Lab install directory>\QII4_0\Lab1\ pipemult
We will now create the design shown in Figure 1.
Step 2 (Build an 8x8 multiplier using the MegaWizard ® Plug-in Manager)
1. Choo Tools ⇒ MegaWizard Plug-In Manager . In the window that appears,
驻厂lect Create a new custom megafunction variation . Click on Next .
2. On page 2a of the MegaWizard , expand the arithmetic folder and lect
LPM_MULT .
3. From the drop down menu lect Stratix II for the device family. Choo Verilog
HDL output.
Name the output file <Quartus II\Lab install directory>\QII4_0\Lab1\mult . Click on Next .
4. On page 3, t the width of the dataa and datab bus to 8 bits. For the remaining
ttings in this window, u the defaults that appear. Select Next .头像可爱女
5. On page 4, choo U default implementation under “Which Multiplier
Implementation should be ud?” Select Next.
6. On page 5, choo Yes, I want an output latency of 2 clock cycles . Click Next .
7. On page 6, the following check boxes should be enabled to generate output files: mult.v mult.bsf
8. Select Finish in the final window that appears. The multiplier is built.
