Micron Parallel NOR Flash Embedded Memory (P30-65nm)
JS28F256P30B/TFx, RC28F256P30B/TFx, PC28F256P30B/TFx,
RD48F4400P0VBQEx, RC48F4400P0VB0Ex,感恩节祝福
水粉颜料怎么洗
PC48F4400P0VB0Ex, PF48F4000P0ZB/TQEx
Features
•High performance
–100ns initial access for Easy BGA
–110ns initial access for TSOP
–25ns 16-word asychronous page read mode
–52 MHz (Easy BGA) with zero WAIT states and 17ns clock-to-data output synchronous burst
辐射降温
read mode
–4-, 8-, 16-, and continuous word options for burst mode
–Buffered enhanced factory programming (BEFP) at 2 MB/s (TYP) using a 512-word buffer
– 1.8V buffered programming at 1.14 MB/s (TYP) using a 512-word buffer
•Architecture
–MLC: highest density at lowest cost
–Asymmetrically blocked architecture
–Four 32KB parameter blocks: top or bottom con-figuration
–128KB main blocks
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–Blank check to verify an erad block
•Voltage and power
–V CC (core) voltage: 1.7V to 2.0V
–V CCQ (I/O) voltage: 1.7V to 3.6V
–Standy current: 65µA (TYP) for 256Mb
–52 MHz continuous synchronous read current: 21mA (TYP), 24mA (MAX)•Security
–One-time programmable register: 64 OTP bits, programmed with unique information from Mi-
cron; 2112 OTP bits available for customer pro-
gramming
–Absolute write protection: V PP = V SS
–Power-transition era/program lockout
–Individual zero-latency block locking
–Individual block lock-down
–Password access
•Software
–25μs (TYP) program suspend
–25μs (TYP) era suspend
–Flash Data Integrator optimized
–Basic command t and extended function Inter-face (EFI) command t compatible
–Common flash interface
•Density and Packaging
–56-lead TSOP package (256Mb only)
–64-ball Easy BGA package (256Mb, 512Mb)
–QUAD+ and SCSP packages (256Mb, 512Mb)
–16-bit wide data bus鲁迅风筝
•Quality and reliabilty
–JESD47 compliant
–Operating temperature: –40°C to +85°C
–Minimum 100,000 ERASE cycles per block
–65nm process technology
Status Register
Read Status Register
To read the status register, issue the READ STATUS REGISTER command at any address.
Status register information is available at the address that the READ STATUS REGISTER,
WORD PROGRAM, or BLOCK ERASE command is issued to. Status register data is auto-
matically made available following a word program, block era, or block lock com-
mand quence. Reads from the device after any of the command quences will out-
put the devices status until another valid command is written (e.g. READ ARRAY com-
mand).
The status register is read using single asynchronous mode or synchronous burst mode裴斯泰洛奇
reads. Status register data is output on DQ[7:0], while 0x00 is output on DQ[15:8]. In
asynchronous mode, the falling edge of OE# or CE# (whichever occurs first) updates
and latches the status register contents. However, when reading the status register in
synchronous burst mode, CE# or ADV# must be toggled to update status data.
The device write status bit (SR7) provides the overall status of the device. SR[6:1]
prent status and error information about the PROGRAM, ERASE, SUSPEND, V PP, and
BLOCK LOCK operations.
Note: Reading the status register is a nonarray READ operation. When the operation oc-
curs in asynchronous page mode, only the first data is valid and all subquent data are
undefined. When the operation occurs in synchronous burst mode, the same data word
requested will be output on successive clock edges until the burst length requirements
are satisfied.
Table 16: Status Register Description
Notes: 1.Default value = 0x80.
2.Always clear the status register prior to resuming ERASE operations. This eliminates sta-
tus register ambiguity when issuing commands during ERASE SUSPEND. If a command
quence error occurs during an ERASE SUSPEND, the status register contains the com-
mand quence error status (SR[7,5,4] t). When the ERASE operation resumes and fin-
ishes, possible errors during the operation cannot be detected via the status register be-
cau it contains the previous error status.
3.When bits 5:4 indicate a PROGRAM/ERASE operation error, either a CLEAR STATUS REG-
ISTER 50h) or a RESET command must be issued with a 15µs delay.
Clear Status Register
The CLEAR STATUS REGISTER command clears the status register. It functions inde-
pendently of V PP. The device ts and clears SR[7,6,2], but it ts bits SR[5:3,1] without
clearing them. The status register should be cleared before starting a command -
quence to avoid any ambiguity. A device ret also clears the status register.
Configuration Register
Read Configuration Register
The read configuration register (RCR) is a 16-bit read/write register ud to lect bus
read mode (synchronous or asynchronous) and to configure device synchronous burst
read characteristics. To modify RCR ttings, u the CONFIGURE READ CONFIGURA-
TION REGISTER command. RCR contents can be examined using the READ DEVICE
IDENTIFIER command and then reading from offt 0x05. On power-up or exit from re-
t, the RCR defaults to asynchronous mode. RCR bits are described in more detail be-
low.
Note: Reading the configuration register is a nonarray READ operation. When the oper-
ation occurs in asynchronous page mode, only the first data is valid, and all subquent
data are undefined. When the operation occurs in synchronous burst mode, the same
word of data requested will be output on successive clock edges until the burst length
requirements are satisfied.
Table 17: Read Configuration Register
Read Mode
The read mode (RM) bit lects synchronous burst mode or asynchronous page mode
operation for the device. When the RM bit is t, asynchronous page mode is lected
(default). When RM is cleared, synchronous burst mode is lected.
Latency Count
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The latency count (LC) bits tell the device how many clock cycles must elap from the
rising edge of ADV# (or from the first valid clock edge after ADV# is asrted) until the
first valid data word is driven to DQ[15:0]. The input clock frequency is ud to deter-
mine this value. The First Access Latency Count figure shows the data output latency for
different LC ttings.
Figure 13: First Access Latency Count
船到江心补漏迟CLK [C]
Address [A]
ADV# [V]
DQ[15:0] [D/Q]
DQ[15:0] [D/Q]
DQ[15:0] [D/Q]
DQ[15:0] [D/Q]
DQ[15:0] [D/Q]
DQ[15:0] [D/Q]
DQ[15:0] [D/Q]
DQ[15:0] [D/Q]
Note: 1.First Access Latency Count Calculation:
•1 / CLK frequency = CLK period (ns)
•n x (CLK period) ≥t AVQV (ns) – t CHQV (ns)
•Latency Count = n
