DABiC-IV , 10-BIT SERIAL-INPUT,LATCHED SOURCE DRIVERS
Data Sheet 26182.124B
The A6809– and A6810– devices combine 10-bit CMOS shift registers, accompanying data latches and control circuitry with bipolar sourcing outputs and pnp active pull downs. Designed primarily to drive vacuum-fluorescent displays, the 60 V and -40 mA output ratings also allow the devices to be ud in many other peripheral power driver applications. The A6809– and A6810– feature an incread data input rate (compared with the older UCN/UCQ5810-F) and a con-trolled output slew rate. The A6809xLW and A6810xLW are identical except for pinout.
The CMOS shift register and latches allow direct interfacing with microprocessor-bad systems. With a 3.3 V or 5 V logic supply,typical rial-data input rates are up to 33 MHz.
A CMOS rial data output permits cascade connections in applica-tions requiring additional drive lines. Similar devices are avail-able as the A6811– (12 bits), A6812– (20 bits), and A6818– (32 bits).
The A6809– and A6810– output source drivers are npn Darling-tons, capable of sourcing up to 40 mA. The controlled output slew rate reduces electromagnetic noi, which is an important consideration in systems that include telecommunications and/or microprocessors and to meet government emissions regulations. For inter-digit blanking, all output drivers can be disabled and all
sink drivers turned on with a BLANKING input high. The pnp active pull-downs will sink at least 2.5 mA.
All devices are available in two temperature ranges for optimum performance in commercial (suffix S-) or industrial (suffix E-) applica-tions. The A6810– is provided in three package styles for through-hole DIP (suffix -A), surface-mount SOIC (suffix -LW), or minimum-area surface-mount PLCC (suffix -EP). The A6809– is provided in the SOIC (suffix -LW) only. Copper lead frames, low logic-power dissi-pation, and low output-saturation voltages allow all devices to source 25 mA from all outputs continuously over the maximum operating temperature range.
FEATURES
I Controlled Output Slew Rate I High-Speed Data Storage I 60 V Minimum Output Breakdown I High Data Input Rate I PNP Active Pull-Downs Complete part number includes a suffix to identify operating temperature range (E- or S-) and package type (-A, -EP, or -LW).Always order by complete part number, e.g., A6810SLW .
6809 AND 6810
I Low Output-Saturation Voltages I Low-Power CMOS Logic and Latches I Improved Replacements for TL4810–, UCN5810–,and UCQ5810–
6809 AND 6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachutts 01615-0036 (508) 853-5000Copyright © 1998, 2000 Allegro MicroSystems, Inc.
A6810xEP
TYPICAL OUTPUT DRIVER
TYPICAL INPUT CIRCUIT
A6809xLW
SERIAL DATA OUT LOAD SUPPLY SERIAL DATA IN BLANKING
OUT 1OUT 2OUT 3
LOGIC SUPPLY
STROBE OUT 5OUT 4
GROUND CLOCK OUT 9OUT 10
Dwg. PP-029-9OUT 8OUT 7OUT 6NO
CONNECTION NO
CONNECTION
A6810xLW
SERIAL DATA OUT LOAD SUPPLY SERIAL DATA IN BLANKING OUT 9OUT 10OUT 1OUT 2OUT 3
NO
CONNECTION
LOGIC SUPPLY
STROBE GROUND CLOCK OUT 8OUT 7OUT 6OUT 5OUT 4脂溢性皮炎脸部怎么治
NO
CONNECTION
Dwg. PP-029-2
STROBE
王羲之小楷Dwg. PP-059
O U T 1
O U T 10
O U T 5
O U T 6 CLOCK
NC
GROUND LOGIC SUPPLY SERIAL DATA OUT LOAD SUPPLY NC SERIAL DATA IN BLANKING
5075100125
150
2.5
0.5
A
L L O W A B L E P A C K A G E P O W E R D I S S I P A T I O N
I N W A T T S
450字的作文
AMBIENT TEMPERATURE IN °C
2.0
1.5
1.0
25
Dwg. GP-024-1
Dwg. EP-010-5
IN
N
6809 AND 6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
TRUTH TABLE
L = Low Logic Level H = High Logic Level X = Irrelevant P = Prent State R = Previous State
LATCHES
6809 AND 6810
掩饰的拼音诺氟沙星胶囊的作用与功效10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachutts 01615-0036 (508) 853-5000美国用英语怎么写
Limits @ V DD = 3.3 V Limits @ V DD = 5 V
Characteristic
Symbol Test Conditions Mln.Typ.Max.Min.Typ.Max.Units Output Leakage Current I CEX V OUT = 0 V —<-0.1-15—<-0.1-15µA Output Voltage
V OUT(1)I OUT = -25 mA 57.558.3—57.558.3—V V OUT(0)
I OUT = 1 mA — 1.0 1.5— 1.0 1.5V Output Pull-Down Current I OUT(0)V OUT = 5 V to V BB
2.5 5.0— 2.5 5.0—mA Input Voltage
V IN(1) 2.2—— 3.3——V V IN(0)
—— 1.1—— 1.7V Input Current
I IN(1)V IN = V DD —<0.01 1.0—<0.01 1.0µA I IN(0)
V IN = 0 V —<-0.01-1.0—<-0.01-1.0µA Input Clamp Voltage V IK I IN = -200 µA —-0.8-1.5—-0.8-1.5V Serial Data Output Voltage
V OUT(1)I OUT = -200 µA 2.8 3.05— 4.5 4.75—V V OUT(0)
I OUT = 200 µA —0.150.3—0.150.3V Maximum Clock Frequency f c 1033—1033—MHz Logic Supp
ly Current
I DD(1)All Outputs High —0.250.75—0.3 1.0mA I DD(0)
All Outputs Low
—0.250.75—0.3 1.0mA Load Supply Current
I BB(1)All Outputs High, No Load — 1.5 3.0— 1.5 3.0mA I BB(0)
All Outputs Low —0.220—0.220µA Blanking -to-Output Delay
t dis(BQ)C L = 30 pF, 50% to 50%—0.7 2.0—0.7 2.0µs t en(BQ)
泡脚多长时间
C L = 30 pF, 50% to 50%— 1.8 3.0— 1.8 3.0µs Strobe -to-Output Delay
t p(STH-QL)R L = 2.3 k Ω, C L ≤ 30 pF —0.7 2.0—0.7 2.0µs t p(STH-QH)
R L = 2.3 k Ω, C L ≤ 30 pF — 1.8 3.0— 1.8 3.0µs Output Fall Time t f R L = 2.3 k Ω, C L ≤ 30 pF 2.4—12 2.4—12µs Output Ri Time t r R L = 2.3 k Ω, C L ≤ 30 pF 2.4—12 2.4—12µs Output Slew Rate
dV/dt
R L = 2.3 k Ω, C L ≤ 30 pF 4.0—20 4.0—20V/µs Clock -to-Serial Data Out Delay t p(CH-SQX)
I OUT = ±200 µA —
50
—
—
景物作文200字50
—
ns
Negative current is defined as coming out of (sourcing) the specified device terminal.Typical data is is for design information only and is at T A = +25°C.
ELECTRICAL CHARACTERISTICS at T A = +25°C (A6809SLW & A6810S-) or over operating temperature range (A6809ELW & A6810E-), V BB = 60 V unless otherwi noted.
6809 AND 6810 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS
TIMING REQUIREMENTS and SPECIFICATIONS (Logic Levels are V DD and Ground)
Serial Data prent at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input pul. On succeeding CLOCK puls, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform.
Information prent at any register is transferred to the respective latch when the STROBE is high (rial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypasd (STROBE tied high) will require that the BLANKING input be high during rial data entry.
When the BLANKING input is high, the output source drivers are disabled (OFF); the pnp active pull-down sink drivers are ON. The information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches.
OUT
Dwg. WP-029
OUT
Dwg. WP-030 A. Data Active Time Before Clock Pul
(Data Set-Up Time), t su(D)......................................... 25 ns
B. Data Active Time After Clock Pul
(Data Hold Time), t h(D)............................................... 25 ns
C. Clock Pul Width, t w(CH)............................................... 50 ns
D. Time Between Clock Activation and Strobe, t su(C)....... 100 ns
E. Strobe Pul Width, t w(STH)............................................. 50 ns
NOTE – Timing is reprentative of a 10 MHz clock. Signifi-
cantly higher speeds are attainable.
6809 AND 6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachutts 01615-0036 (508) 853-5000
A6810EA & A6810SA
Dimensions in Inches (controlling dimensions)
Dimensions in Millimeters (for reference only)
NOTES:1.Exact body and lead configuration at vendor ’s option within limits shown.
2.Lead spacing tolerance is non-cumulative.
3.Lead thickness is measured at ating plane or below.
Dwg. MA-001-18A in
Dwg. MA-001-18A mm
