MultiTrack Interconnect
Clear & Pret Logic Control
LAB-wide signals control the logic for the register's clear and load/pret
signals. The ALM directly supports an asynchronous clear and pret
function. The register pret is achieved through the asynchronous load
of a logic high. The direct asynchronous pret does not require a NOT-
gate push-back technique. Stratix II devices support simultaneous
asynchronous load/pret, and clear signals. An asynchronous clear
signal takes precedence if both signals are asrted simultaneously. Each
LAB supports up to two clears and one load/pret signal.
In addition to the clear and load/pret ports, Stratix II devices provide a
device-wide ret pin (DEV_CLRn) that rets all registers in the device.
An option t before compilation in the Quartus II software controls this
pin. This device-wide ret overrides all other control signals.
MultiTrack Interconnect In the Stratix II architecture, connections between ALMs, TriMatrix memory, DSP blocks, and device I/O pins are provided by the MultiTrack interconnect structure with DirectDrive TM technology. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths and speeds ud for inter- and intra-design block connectivity. The Quartus II Compiler automatically places critical design paths on faster interconnects to improve design performance. DirectDrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement in the device. The MultiTrack interconnect and DirectDrive technology simplify the integration stage of block-bad designing by eliminating the re-optimization cycles that typically follow design changes and additions.
The MultiTrack interconnect consists of row and column interconnects that span fixed distances. A routing structure with fixed length resources for all devices allows predictable and repeatable perfor
mance when migrating through different device densities. Dedicated row interconnects route signals to and from LABs, DSP blocks, and TriMatrix memory in the same row. The row resources include:
■Direct link interconnects between LABs and adjacent blocks
■R4 interconnects traversing four blocks to the right or left
阅读教学■R24 row interconnects for high-speed access across the length of the device
30首月亮古诗
Similar to all RAM blocks, M-RAM blocks can have different clocks on
their inputs and outputs. Either of the two clocks feeding the block can
clock M-RAM block registers (renwe, address, byte enable, datain, and
output registers). The output register can be bypasd. The six labclk
signals or local interconnect can drive the control signals for the A and B
ports of the M-RAM block. ALMs can also control the clock_a,
clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and
clocken_b signals as shown in Figure2–23.
Figure2–23.M-RAM Block Control Signals
The R4, R24, C4, and direct link interconnects from adjacent LABs on欲壑
either the right or left side drive the M-RAM block local interconnect. Up
to 16 direct link input connections to the M-RAM block are possible from
the left adjacent LABs and another 16 possible from the right adjacent
LAB. M-RAM block outputs can also connect to left and right LABs
through direct link interconnect. Figure2–24 shows an example floorplan
for the EP2S130 device and the location of the M-RAM interfaces.
酸奶可以加热喝吗Figures2–25 and 2–26 show the interface between the M-RAM block and
the logic array.
I/O Structure
Stratix II Architecture Figure2–56.DQS Pha-Shift Circuitry Notes(1), (2), (3), (4)
Notes to Figure2–56:
(1)There are up to 18 pairs of DQS and DQSn pins available on the top or the bottom of the Stratix II device. There are
up to 10 pairs on the right side and 8 pairs on the left side of the DQS pha-shift circuitry.
工作后入党申请书(2)The t module reprents the DQS logic block.
(3)Clock pins CLK[15..12]p feed the pha-shift circuitry on the top of the device and clock pins CLK[7..4]p feed
the pha circuitry on the bottom of the device. You can also u a PLL clock output as a reference clock to the pha-shift circuitry.
(4)You can only u PLL 5 to feed the DQS pha-shift circuitry on the top of the device and PLL 6 to feed the DQS
pha-shift circuitry on the bottom of the device.
The dedicated circuits combined with enhanced PLL clocking and
pha-shift ability provide a complete hardware solution for interfacing
to high-speed memory.
f For more information on external memory interfaces, refer to the
External Memory Interfaces in Stratix II & Stratix II GX Devices chapter in
volume 2 of the Stratix II Device Handbook or the Stratix II GX Device
Handbook.
Programmable Drive Strength
The output buffer for each Stratix II device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL, LVCMOS,
SSTL, and HSTL standards have veral levels of drive strength that the
ur can control. The default tting ud in the Quartus II software is the
maximum current strength tting that is ud to achieve maximum I/O
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performance. For all I/O standards, the minimum tting is the lowest
农历腊月是几月
桌面的英文drive strength that guarantees the I OH/I OL of the standard. Using
minimum ttings provides signal slew rate control to reduce system
noi and signal overshoot.
