菠萝水果茶1FS ADJUST Full-Scale Adjust Control.A resistor(RSET)is connected between this pin and AGND.This determines the magnitude
of the full-scale DAC current.The relationship between RSET and the full-scale current is as follows:
IOUT=18×V/R
FULL SCALE REFOUT SET
V=1.20V nominal,R=6.8 kΩtypical.
REFOUT SET
2REFOUT Voltage Reference Output.The AD9834has an internal1.20V reference that is made available at this pin.
3COMP DAC Bias Pin.This pin is ud for decoupling the DAC bias voltage.
17VIN Input to Comparator.The comparator can be ud to generate a square wave from the sinusoidal DAC output.The
DAC output should be filtered appropriately before being applied to the comparator to improve jitter.When Bit
OPBITEN and Bit SIGNPIB in the control register are t to1,the comparator input is connected to VIN.
19,20IOUT,Current Output.This is a high impedance current source.
A load resistor of nominally200Ωshould be connected
IOUTB between IOUT and AGND.IOUTB should preferably be tied through an external load resistor of200Ωto AGND,but
后浪
it can be tied directly to AGND.A20pF capacitor to AGND is also recommended to prevent clock feedthrough.
POWER SUPPLY
4AVDD Positive Power Supply for the Analog Section.AVDD can have a value from2.3V to5.5V.A0.1μF decoupling
capacitor should be connected between AVDD and AGND.
5DVDD Positive Power Supply for the Digital Section. DVDD can have a value from2.3V to5.5V.A0.1μF decoupling
capacitor should be connected between DVDD and DGND.
6CAP/2.5V The digital circuitry operates from a2.5V power supply.This2.5V is generated from DVDD using an on-board
regulator(when DVDD exceeds2.7V).The regulator requires a decoupling capacitor of typically100nF that is
connected from CAP/2.5V to DGND.If DVDD is equal to or less than2.7V,CAP/2.5V should be shorted to DVDD.
7DGND Digital Ground.
18AGND Analog Ground.
DIGITAL INTERFACE AND CONTROL
8MCLK Digital Clock Input.DDS output frequencies are expresd as a binary fraction of the frequency of MCLK.The
output frequency accuracy and pha noi are determined by this clock.
9FSELECT Frequency Select Input.FSELECT controls which frequency register,FREQ0or FREQ1,is ud in the pha
accumulator.The frequency register to be ud can be lected using Pin FSELECT or Bit FSEL.When Bit FSEL is
ud to lect the frequency register,the FSELECT pin should be tied to CMOS high or low.
10PSELECT Pha Select Input.PSELECT controls which pha register,PHASE0or PHASE1,is added to the pha accumulator
output.The pha register to be ud can be lected using Pin PSELECT or Bit PSEL.When the pha registers are being
controlled by Bit PSEL,the PSELECT pin should be tied to CMOS high or low.
11RESET Active High Digital Input.RESET rets appropriate internal registers to zero;this corresponds to an analog output
of midscale.RESET does not affect any of the addressable registers.
12SLEEP Active High Digital Input.When this pin is high,the DAC is powered down.This pin has the same function as
Control Bit SLEEP12.
1FS调整满量程的调节控制。此引脚与AGND之间连接一个电阻（RSET）。这就决定了幅度
满量程DAC电流。RSET和满量程电流之间的关系如下：
IOUT=18×V/R
全尺寸REFOUT集
V=1.20V标称值，R=达观的意思
6.8kΩ的典型。
REFOUT设定
云南信息报
2REFOUT参考电压输出。AD9834有一个是在此引脚的内部1.20 V参考。三月六日
3COMP DAC偏置引脚。此引脚用于去耦DAC的偏置电压。
17VIN输入比较器。比较器可用于生成一个正弦DAC输出的方波。“
应适当进行过滤，然后被应用到比较完善的抖动DAC输出。当位
OPBITEN和控制寄存器SIGNPIB的设置为1，比较器的输入连接到VIN。
19日，20输出电流，电流输出。这是一个高阻抗电流源。一个名义上的200Ω的负载电阻应接
IOUTB之间IOUT和AGND。IOUTB应最好是通过外部负载电阻200Ω至AGND并列，但
它可以直接连接到AGND。一个20pF的电容连接到AGND还建议，以防止时钟馈通。
电源供应器
4AVDD的模拟部分的电源正极。AVDD的可以有一个值从2.3V至5.5V的0.1μF的去耦
电容应连接AVDD和AGND 之间。
5DVDD数字部分的电源正极。DVDD可以有一个值从2.3V至5.5 V的0.1μF的去耦
电容应连接的DVDD和DGND之间。
新经济地理学6CAP/2.5V数字电路从2.5V电源。使用一个板上，这个2.5V是从DVDD的生成
稳压器（DVDD超过2.7V 时）。该稳压器需要一个通常为100nF的去耦电容器，
从CAP/2.5V连接到DGND。如果DVDD是等于或小于2.7V时，CAP/2.5V应该到DVDD短路。7DGND数字地。
18AGND模拟地。
数字接口和控制
8MCLK的数字时钟输入。DDS输出频率表示二进制小数的MCLK 频率。“
是由这个时钟输出频率精度和相位噪声。
9F选择频率选择输入。F选择控制频率寄存器，FREQ0或FREQ1，是相
累加器。频率寄存器，可以选择使用引脚FSELECT或位FSEL要使用。当位FSEL
用来选择频率寄存器，F选择
引脚应连接到CMOS高或低。
10PSELECT阶段选择输入。PSELECT相位寄存器，PHASE0或PHASE1，被添加到相位累加器控制
输出。相位寄存器被使用，可以选择使用引脚PSELECT或位PSEL。当相位寄存器
位PSEL控制，PSELECT引脚应连接到CMOS高或低。
11复位高电平数字输入。RESET复位适当的内部寄存器为零；此相对应的模拟输出
的中点。复位不影响任何寻址寄存器。
12休眠高电平数字输入。当此引脚为高电平时，DAC断电。该引脚具有相同的功能
控制位SLEEP12。
DB13B28Two write operations are required to load a complete word into either of the frequency registers.
B28=1allows a complete word to be loaded into a frequency register in two concutive writes.The first write
contains the14LSBs of the frequency word and the next write contains the14MSBs.The first two bits of each
16-bit word define the frequency register the word is loaded to and should,therefore,be the same for both of the
concutive writes.Refer to Table10for the appropriate address.The write to the frequency register occurs after
both words have been loaded.An example of a complete28-bit write is shown in Table11.Note however,that
concutive28-bit writes to the same frequency register are not allowed,switch between frequency registers to do
this type of function.
B28=0,the28-bit frequency register operates as two 14-bit registers,one containing the14MSBs and the other
containing the14LSBs.This means that the14MSBs of the frequency word can be altered independent of the
14LSBs,and vice versa.To alter the14MSBs or the14 LSBs,a single write is made to the appropriate frequency
address.The Control Bit DB12(HLB)informs the AD9834whether the bits to be altered are the14MSBs or14LSBs.
DB12HLB This control bit allows the ur to continuously load the MSBs or LSBs of a frequency register ignoring the remaining
14bits.This is uful if the complete28-bit resolution is not required.HLB is ud in conjunction with DB13(B28).This
control bit indicates whether the14bits being loaded are being transferred to the14MSBs or14LSBs of the addresd
frequency register.DB13(B28)must be t to0to be able to change the MSBs and LSBs of a frequency word parately.
When DB13(B28)=1,this control bit is ignored.小狗不能吃什么
HLB=1allows a write to the14MSBs of the addresd frequency register.
HLB=0allows a write to the14LSBs of the addresd frequency register.
DB11FSEL The FSEL bit defines whether the FREQ0register or the FREQ1register is ud in the pha accumulator.See Table8to
lect a frequency register.
DB10PSEL The PSEL bit defines whether the PHASE0register data or the PHASE1register data is added to the output of the pha
accumulator.See Table9to lect a pha register.
风景旧曾谙DB9PIN/SW Functions that lect frequency and pha registers,ret internal registers,and power down the DAC can be
