=
+2.5 V to +5.5 V, 25 MHz Low Power
CMOS C omplete D DS脸部消肿
Preliminary T echnical D ata AD9833
FEATURES
+2.3 V to +5.5 V Power Supply 25 MHz Speed
Tiny 10-Pin µSOIC Package Serial Loading
Sinusoidal/Triangular DAC Output Power-Down Option
Narrowband SFDR > 72 dB
20 mW Power Consumption at 3 V APPLICATIONS Digital Modulation Portable Equipment Test Equipment DDS Tuning
鬼刀手机壁纸
FUNCTIONAL BLOCK DIAGRAM
醋泡黑豆功效GENERAL DESCRIPTION
This low power DDS device is a numerically controlled oscillator employing a pha accumulator, a SIN ROM and a 10-bit D/A converter integrated on a single
CMOS chip. Clock rates up to 25 MHz are supported
with a power supply from +2.3 V to +5.5 V.
Capability for pha modulation and frequency modula-tion is provided. Frequency accuracy can be controlled to
one part in 0.25 billion. Modulation is effected by loading registers through the rial interface.
The AD9833 offers a variety of output waveforms from the VOUT pin. The SIN ROM can be bypasd so that a linear up/down ramp is output from the DAC. If the SIN ROM is not by-pasd, a sinusoidal output is available.Also, if a clock output is required, the MSB of the DAC data can be output.
The digital ction is internally operated at +2.5 V, irre-spective of the value of VDD, by an on board regulator which steps down VDD to +2.5 V, when VDD exceeds +2.5 V.
The AD9833 has a power-down function (SLEEP). This allows ctions of the device which are not being ud to be powered down, thus minimising the current consump-tion of the part e.g the DAC can be powered down when a clock output is being generated.
The AD9833 is available in a 10-pin µSOIC package.
PRELIMINARY TECHNICAL DATA
REV PrG 02/02
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its u, nor for any infringements of patents or other rights of third parties which may result from its u. No licen is granted by implication or otherwi under any patent or patent rights of Analog Devices.柚子皮的功效与作用
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,U.S.A.Tel: 781/329-4700 Fax: 781/326-8703© Analog Devices, Inc., 2002
AD9833
–2–REV PrG
PRELIMINARY TECHNICAL DATA
Parameter
Min
Typ
Max Units
Test Conditions/Comments
SIGNAL DAC SPECIFICATIONS Resolution
10
Bits Update Rate (f MAX )25MSPS Output Compliance 20.8
V DC Accuracy:
Integral Nonlinearity ±1LSB Differential Nonlinearity
±0.5
LSB
DDS SPECIFICATIONS Dynamic Specifications:Signal to Noi Ratio 50
dB f MCLK = 25 MHz, f OUT = 1.5 kHz Total Harmonic Distortion
-53
dBc f MCLK = 25 MHz, f OUT = 1.5 kHz Spurious Free Dynamic Range (SFDR):Wideband (± 2 MHz)50dBc f MCLK = 25 MHz, f OUT = f MCLK /355dBc f MCLK = 25 MHz, f OUT = 0.5 MHz NarrowBand (± 50 kHz)72dBc f MCLK = 25 MHz, f OUT = f MCLK /375
dBc f MCLK = 25 MHz, f OUT = 0.5 MHz
Clock Feedthrough –55dBc Wake Up Time 1ms OUTPUT BUFFER Output Ri/Fall Time 20ns Using a 15 pF Load
Output Jitter
100ps rms When DAC data MSB is output VOLTAGE REFERENCE Internal Reference 1.116 1.2
1.284
V 1.2 V ± 7%
LOGIC INPUTS
V INH , Input High Voltage
V DD –0.9V +3.6 V to +5.5 V Power Supply V DD - 0.5V +2.7 V to +3.6 V Power Supply 2
V +2.3 V to + 2.7 V Power Supply V INL , Input Low Voltage 0.9V +3.6 V to +5.5 V Power Supply 0.5V +2.3 V to + 3.6 V Power Supply
I INH , Input Current 1µA C IN , Input Capacitance 10pF POWER SUPPLIES f MCLK = 25 MHz, f OUT = f MCLK /7
VDD 2.3
5.5V I AA 35mA I DD 3
1 + 0.04/MHz mA I AA + I DD 3
710mA 3 V Power Supply 1015
mA 5 V Power Supply
Low Power Sleep Mode 3
0.25
mA
DAC and Internal Clock Powered Down
NOTES 1
Operating temperature range is as follows: B Version: –40°C to +85°C; typical specifications are at 25؇C 2
Guaranteed by Design.3番茄汤
Measured with the digital inputs static and equal to 0 V or DVDD.
Specifications subject to change without notice. There is 95% test coverage of the digital circuitry.
SPECIFICATIONS
1
(V DD = +2.3 V to +5.5 V; AGND = DGND = 0 V; T A = T MIN to T MAX ; R SET = 6.8k Ω for
VOUT unless otherwi noted)
AD9833
–3–
REV PrG PRELIMINARY TECHNICAL DATA
T IMING C HARACT ERIST ICS 1
(V DD = +2.3 V to +5.5 V; AGND = DGND = 0 V, unless otherwi noted)
Parameter Limit at T MIN to T MAX Units Test Conditions/Comments
t 140ns min MCLK Period
t 216ns min MCLK High Duration t 316ns min MCLK Low Duration t 425ns min SCLK Period
t 510ns min SCLK High Duration t 610ns min SCLK Low Duration
t 75ns min FSYNC
to SCLK Falling Edge Setup Time t 810ns min FSYNC to SCLK Hold Time t 4 - 5ns max t 95ns min Data Setup Time t 10
3
ns min
Data Hold Time
1
Guaranteed by design, not production tested.
Figure 2.Master Clock
Figure 3.Serial Timing
SCLK
FSYNC
SDATA
Figure 1.Test Circuit With which Specifications are tested.
景观效果图
CAUTION
ESD (electrostatic discharge) nsitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection.Although the AD9833 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
AD9833
–4–REV PrG
PRELIMINARY TECHNICAL DATA
ABSOLUTE MAXIMUM RATINGS*
(T A = +25°C unless otherwi noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V VDD to DGND . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V AGND to DGND. . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V CAP/2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.75 V Digital I/O Voltage to DGND .–0.3 V to VDD + 0.3 V Analog I/O Voltage to AGND .–0.3 V to VDD + 0.3 V Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . .–40°C to +85°C Storage Temperature Range . . . . . . . . .–65°C to +150°C
PIN CONFIGURATION Maximum Junction Temperature . . . . . . . . . . . . . .150°C
µSOIC Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . .206°C/W θJC Thermal Impedance . . . . . . . . . . . . . . . . . . .44°C/W Lead Temperature, Soldering (10 c) . . . . . . . . .300°C IR Reflow, Peak Temperature . . . . . . . . . . . . . . .220°C
*Stress above tho listed under “Absolute Maximum Ratings” may cau permanent damage to the device. This is a stress rating only and functional operation of the device at the or any other conditions above tho listed in the operational ctions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
Temperature Range Package Description
Package Option AD9833BRM
–40°C to +85°C
50万韩币
14-Pin µSOIC (Micro Small Outline IC )RM-10
EVAL-AD9833EB
Evaluation Board
VDD CAP/2.5V
DGND MCLK
COMP PIN DESCRIPTION
Pin #Mnemonic Function
POWER SUPPLY 2VDD
Positive power supply for the analog ction and the digital interface ctions. The on board 2.5 V regulator is also supplied from VDD. VDD can have a value from +2.3 V to +5.5 V. A 0.1 µF and 10 µF decoupling capacitor should be connected between VDD and AGND.
3CAP/2.5V The digital circuitry operates from a +2.5 V power supply. This +2.5 V is generated from VDD
using an on board regulator (when VDD exceeds +2.7 V). The regulator requires a decoupling capacitor of typically 100 nF, which is connected from CAP/2.5V to DGND. If VDD is equal to or less than +2.7 V, CAP/2.5V should be tied directly to VDD.
4DGND Digital Ground.9AGND Analog Ground.ANALOG SIGNAL AND REFERENCE 1COMP A D
AC Bias Pin. This pin is ud for de-coupling the DAC bias voltage.10VOUT Voltage Output. The analog and digital output from the AD9833 is available at this pin. An
external load resistor is not required as the device has a 200W resistor on board.
DIGITAL INTERFACE AND CONTROL 5MCLK Digital Clock Input. DDS output frequencies are expresd as a binary fraction of the frequency of
MCLK. The output frequency accuracy and pha noi are determined by this clock.
6SDATA Serial Data Input. The 16-bit rial data word is applied to this input.7SCLK Serial Clock Input. Data is clocked into the AD9833 on each falling SCLK edge.8FSYNC Active Low Control Input. This is the frame synchronisation signal for the input data. When
FSYNC is taken low, the internal logic is informed that a new word is being loaded into the device.
AD9833
–5–
REV PrG PRELIMINARY TECHNICAL DATA
T ypical Performance Characteristics
TBD TPC 1. Typical Current Consumption钢铁之魂
vs. MCLK Frequency TBD TPC 4. Wide Band SFDR vs. f OUT /f MCLK
for Various MCLK Frequencies
TBD
TPC 7. Wake-Up Time vs.
Temperature
TBD TPC 2. Narrow Band SFDR vs. MCLK
Frequency TBD TPC 5. SNR vs. MCLK Frequency
TBD
TPC 3. Wide Band SFDR vs. MCLK
Frequency
TBD
TPC 6. SNR vs. f OUT /f MCLK for Various MCLK Frequencies
AD9833
–6–REV PrG
PRELIMINARY TECHNICAL DATA
T ypical Performance Characteristics
TBD TPC 9. f MCLK = 10 MHz; f OUT = 2.4 kHz;
Frequency Word = 000FBA9
TBD TPC 12. f MCLK = 25 MHz; f OUT = 6 kHz;
Frequency Word = 000FBA9TBD TPC 15. f MCLK = 25 MHz;
f OUT = 2.4 MHz;
Frequency Word = 189374D TBD TPC 10. f MCLK = 10 MHz; f OUT = 1.43 kHz
= f MCLK /7 ;
Frequency Word = 2492492TBD TPC 13. f MCLK = 25 MHz; f OUT = 60 kHz;
Frequency Word = 009D495TBD TPC 16. f MCLK = 25 MHz;f OUT = 3.857 MHz = f MCLK /7 ;Frequency Word = 277EE4F TBD
TPC 11. f MCLK = 10 MHz; f OUT = 3.33 kHz
= f MCLK /3 ;
Frequency Word = 5555555
TBD
TPC 14. f MCLK = 25 MHz; f OUT = 600 kHz;
Frequency Word = 0624DD3
TBD
TPC 17. f MCLK = 25 MHz;f OUT = 8.333 MHz = f MCLK /3 ;Frequency Word = 555475C
