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STE100P
February 2006
1
DESCRIPTION
The STE100P, also referred to as STEPHY1, is a high performance Fast Ethernet physical layer in-terface for 10Ba-T and 100Ba-TX applica-tions.
It was designed with advanced CMOS technology to provide a Media Independent Interface (MII) for easy attachment to 10/100 Media Access Control-lers (MAC) and a physical media interface for 100Ba-TX of IEEE802.3u and 10Ba-T of IEEE802.3.
The STEPHY1 supports both half-duplex and full-duplex operation, at 10 and 100 Mbps operation.Its operating mode can be t using auto-negotia-tion, parallel detection or manual control. It also al-lows for the support of auto-negotiation functions for speed and duplex detection.
2FEATURES
2.1Industry standard
■IEEE802.3u 100Ba-TX and IEEE802.3 10Ba-T compliant ■Support for IEEE802.3x flow control
■
IEEE802.3u Auto-Negotiation support for 10Ba-T and 100Ba-TX ■MII interface
■
Standard CSMA/CD or full duplex operation supported
■
Industrial temperature compliant
10/100 FAST ETHERNET 3.3V TRANSCEIVER
Figure 2. Block Diagram
Rev. 19
Figure 1. Package
Table 1. Order Codes
(*) ECOPACK® (e Section 9)
Part Number Package STE100P TQFP64E-STE100P (*)
TQFP64
STE100P
2.2Physical Layer
■Integrates the whole Physical layer functions of 100Ba-TX and 10Ba-T外墙外保温
■Provides Full-duplex operation on both 100Mbps and 10Mbps modes
■Provides Auto-negotiation(NWAY) function of full/half duplex operation for both 10 and 100 Mbps ■Provides MLT-3 transceiver with DC restoration for Ba-line wander compensation
■Provides transmit wave-shaper, receive filters, and adaptive equalizer
■Provides loop-back modes for diagnostic
■Builds in Stream Cipher Scrambler/ De-scrambler and 4B/5B encoder/decoder
■Supports external transmit transformer with turn ratio 1:1
■Supports external receive transformer with turn ratio 1:1
2.3LED Display
The LED display, consists of five LEDs having the following characteristics:
■10 Mbps Speed LED: 10Mbps(on) or 100Mbps(off)
■100 Mbps Speed LED: 100Mbps(on) or 10Mbps(off)
■TX/RX Activity LED: Blinks at 10Hz when receiving, but not colliding
■Link LED: On when a good link is detected, blinks when there is TX or RX activity
■Full Duplex / Collision LED: On during Full Duplex operation. Blinks at 20Hz to indicate a collision 2.4Miscellaneous
■Standard 64-pin QFP package pinout
Figure 3. System Diagram of the STE100P Application
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STE100P 3PIN ASSIGNMENT DIAGRAM
Figure 4. Pin Connection
4PIN DESCRIPTION
Table 2. Pin Description
Pin No.Name Type Description
MII Data Interface
52 58 57 56 55txd4
txd3
txd2
txd1
txd0
I Transmit Data. The Media Access Controller (MAC) drives data to the STE100P
using the inputs.
txd4 is monitored only in Symbol (5B) Mode.
The signals must be synchronized to the tx_clk.
54tx_en I Transmit Enable. The MAC asrts this signal when it drives valid data on the
txd inputs. This signal must be synchronized to the tx_clk.
53tx_clk I/O Transmit Clock. Normally the STE100P drives tx_clk. Refer to the Clock
Requirements discussion in the Functional Description ction.
25 MHz for 100 Mbps operation.
2.5 MHz for 10 Mbps operation.
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STE100P
4/31
52
tx_er
I
Transmit Coding Error . The MAC asrts this input when an error has occurred in the transmit data stream. When the STE100P is operating at 100 Mbps, the STE100P responds by nding invalid code symbols on the line. In Symbol (5B)Mode this pin functions as txd4.
5143444647rxd4rxd3rxd2rxd1rxd0O
Receive Data . The STE100P drives received data on the outputs, synchro-nous to rx_clk.
挽救的反义词
rxd4 is driven only in Symbol (5B) Mode.
48rx_dv O Receive Data Valid . The STE100P asrts This signal when it drives valid data on rxd. This output is synchronous to rx_clk.
51
rx_er
O
Receive Error . The STE100P asrts this output when it receives invalid sym-bols from the network. This signal is synchronous to rx_clk. In Symbol (5B) Mode this pin functions as rxd4.
49rx_clk O
Receive Clock . This continuous clock provides reference for rxd, rx_dv, and rx_er signals. Refer to the Clock Requirements discussion in the Functional Description ction.
25 MHz for 100 Mbps operation.2.5 MHz for 10 Mbps operation.
59col O
Collision Detected . The STE100P asrts this output when detecting a collision.This output remains High for the duration of the collision. This signal is asynchro-nous and inactive during full-duplex operation.
60crs O
Carrier Sen . During half-duplex operation (PR0:8=0), the STE100P asrts this output when either transmit or receive medium is non idle. During full duplex operation (PR0:8=1), crs is asrted only when the receive medium is non-idle.
MII Control Interface 42mdc I Management Data Clock . Clock for the mdio rial data channel. Maximum frequency is 2.5 MHz.
41mdio I/O Management Data Input/Output , Bi-directional rial data channel for PHY communication.
61
mdint
OD
Management Data Interrupt. When any bit in PR18 = 1, an active High output on this pin indicates status change in the corresponding bits in PR17.
Interrupt is cleared by reading Register PR17. Requires MDC edge to output.
P hysical (Twisted Pair) Interface 12
x1
I
25 MHz reference clock input. When an external 25 MHz crystal is ud, this pin will be connected to one terminal of it. If an external 25 MHz clock source of oscillator is ud, then this pin will be the input pin of it.
11x2O
25 MHz reference clock output. When an external 25MHz crystal is ud, this pin will be connected to another terminal of if. If an external clock source is ud, then this pin should be left open.
2123txp txn O The differential Transmit outputs of 100Ba-TX or 10Ba-T , the pins directly output to the transformer.
1918
rxp rxn
I
The differential Receive inputs of 100Ba-TX or 10Ba-T , the pins directly input from the transformer.
Table 2. Pin Description (continued)
Pin No.Name Type Description
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STE100P
话筒支架
15iref O Reference Resistor connecting pin for reference current, directly connect a 5K Ω ± 1% resis
tor to Vss.
38
ledr10
I/O
LED display for 10Ms/s link status. This pin will be driven on continually when 10Mb/s network operating speed is detected.
The pull-up/pull-down status of this pin is latched into the PR20 bit 7 during power up/ret.
37ledtr
LED display for Tx/Rx Activity status. This pin will be driven on at a 10 Hz blinking frequency when either effective receiving or transmitting is detected.
The status of this pin is latched into the PR20 bit 6 during power up/ret.
36ledl
I/O
LED display for Link Status. Blinks when there is TX or RX activity. This pin will be driven on continually when a good Link test is detected.
The status of this pin is latched into the PR20 bit 5 during power up/ret.35ledc I/O
LED display for Full Duplex or Collision status. This pin will be driven on
continually when a full duplex configuration is detected. This pin will be driven on at a 20 Hz blinking frequency when a collision status is detected in the half duplex configuration.
The status of this pin is latched into the PR20 bit 4 during power up/ret.34leds I/O
LED display for 100Ms/s link status. This pin will be driven on continually when 100Mb/s network operating speed is detected.
The status of this pin is latched into the PR20 bit 3 during power up/ret.64cfg0 I
Configuration Control 0.
When A/N is enabled , cfg0 determines operating mode advertiment capabilities in combination with cfg1 when mf0/ PR0:12 =1. (See T able 2)When A/N is disabled , cfg1 disables mlt3 and directly affects PR19:0When cfg0 is Low, mlt3 encoder/decoder is enabled and PR19:1 =0. When cfg0 is High, mlt3 encoder/decoder is bypasd and PR19:1 = 1.
陈佳辉63cfg1I
Configuration Control 1.
When A/N is enabled , cfg1 determines operating mode advertiment capabilities in combination with cfg1 when mf0/ PR0:12 =1. (See T able 2)
When A/N is disabled , CFG1 enables Loopback mode and directly affects PR0 bit 14.
When cfg1 is Low, Loopback mode is disabled and PR0:14 = 0.When cfg1 is High, Loopback mode is enabled and PR0:14 = 1.
28ret I
Ret (Active-Low). This input must be held low for a minimum of 1 ms to ret the STE100P . Durin
g Power-up, the STE100P will be ret regardless of the state of this pin, and this ret will not be complete until after >1ms.
29rip O
Ret In Progress . This output is ud to indicate when the device has completed power-up/ret and the registers and functions can be accesd.When rip is High, power-up/ret has been successful and the device can be ud normally
When rip is Low, device ret is not complete.8, 30,31,32nc nc (No Connection)
26, 33test, test_ T est pins. Should be tied to ground for normal operation
27
pwrdwn
I
Power Down . When High, forces STE100P into Power Down mode. This pin is OR’ed with the Powe
桂林熊虎山庄r Down bit (PR0:11). During the Power Down mode, txp/txn outputs and all LED outputs are 3-stated, and the MII interface is isolated.
Table 2. Pin Description (continued)
Pin No.Name Type Description
STE100P
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5
4321
mf0mf1mf2mf3mf4
I
Multi-Function pins. Each mf pin internally drives different configuration functions. The functions of the five mf inputs are as shown in the table below.
The logic level of mf0-4 will determine the value that the affected bits will have upon ret of the STE100P . The operating functions of cfg0, cfg1, and fde change depending on the state of mf0 (Auto-Negotiation enabled or disabled). T able 2 shows the relationship between cfg0, cfg1 and fde.
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家用笔记本电脑推荐
fde
I
Full-Duplex Enable .
When A/N is enabled , fde determines full-duplex advertiment capability in combination with cfg0 and cfg1. (See T able 2)
提高的同义词When A/N is disabled , fde directly affects full-duplex operation and determines the value of PR0 bit 8 (Full/Half Duplex Mode Select).When fde is High, full-duplex is enabled and PR0:8 = 1.When fde is Low, full-duplex is disabled and PR0:8 = 0.
Digital Power Pins
胖的反义词
39, 45, 62 vcce, vcce/i 25, 40, 50 gnde, gnde/i
Analog Power Pins 9, 13, 16, 17, 22 vcca 7, 10, 14, 20, 24
gnda Table 2. Pin Description (continued)
Pin No.Name Type Description
