post code（开机自检代码）
代码 bios或 3000 BIOS
00. 已显示系统的配置; 即将控制ini19引导装入..
01 处理器测试1, 处理器状态核实, 如果测试失败, 循环是无限的. 处理器寄存器的测试即将开始, 不可屏蔽中断即将停用. Cpu寄存器测试正在进行或者失败.
02 确定诊断的类型 (正常或者制造).如果键盘缓冲器含有数据就会失效. 停用不可屏蔽中断; 通过延迟开始. Cmos写入／读出正在进行或者失灵.
03 清除8042键盘控制器, 发出命令 (AAH) 通电延迟已完成. Rom bios检查部件正在进行或失灵.
04 使8042键盘控制器复位, 核实. 键盘控制器软复位／通电测试. 可编程间隔计时器的测试正在进行或失灵.
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05 如果不断重复制造测试1至5, 可获得8042控制状态. 已确定软复位／通电; 即将启动rom. Dma初如准备正在进行或者失灵.
06 使电路片作初始准备, 停用视频、奇偶性、dma电路片, 以及清除dma电路片, 所有页面寄存器和cmos停机字节. 已启动rom计算检查总和, 以及检查键盘缓冲器是否清除. Dma初始页面寄存器读／写测试正在进行或失灵.
07 处理器测试2, 核实cpu寄存器的工作. 检查总和正常, 键盘缓冲器已清除, 向键盘发出bat (基本保证测试) 命令..
08 使cmos计时器作初始准备, 正常的更新计时器的循环. 已向键
盘发出bat命令, 即将写入bat命令. Ram更新检验正在进行或失灵.
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09 检查总和且必须等于零才通过. 核实键盘的基本保证测试, 接着核实键盘命令字节. 第一个64测试正在进行.
使视频接口作初始准备 0A. 发出键盘命令字节代码, 即将写入命令字节数据. 第一个64芯片或数据线失灵, 移位.
测试8254通道0 0B. 写入键盘控制器命令字节, 即将发出引脚23和24的封锁／解锁命令. 第一个64奇／偶逻辑失灵.
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测试8254通道1 0C. 键盘控制器引脚23、24已封锁／解锁; 已发出nop命令. 第一个64的地址线故障.
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1、检查cpu速度是否与系统时钟相匹配.
2、检查控制芯片已编程值是否符合初设置.
3、视频通道测试 0D, 如果失败, 则鸣喇叭. 已处理nop命令; 第一个64的奇偶性失灵接着测试cmos停开寄存器.
测试cmos停机字节 0E. Cmos停开寄存器读／写测试; 将计算cmos 检查总和. 初始化输入／输出端口地址.
测试扩展的cmos 0f. 已计算cmos检查总和写入诊断字节; cmos开始初始准备..
10 测试dma通道0. Cmos已作初始准备, cmos状态寄存器即将为日期和时间作初始准备. 第一个64第0位故障.
11 测试dma通道1. Cmos状态寄存器已作初始准备, 即将停用dma 和中断控制器. 第一个64第1位故障.
12 测试dma页面寄存器. 停用dma控制器1以及中断控制器1和2;
即将视频显示器并使端口b作初始准备. 第一个64第2位故障.
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可怜无定河边骨13 测试8741键盘控制器接口. 视频显示器已停用, 端口b已作初始准备; 即将开始电路片初始化／存储器自动检测. 第一个64第3位故障.
14 测试存储器更新触发电路. 电路片初始化／存储器处自动检测结束; 8254计时器测试即将开始. 第一个64第4位故障.
15 测试开头64k的系统存储器. 第2通道计时器测试了一半; 8254第2通道计时器即将完成测试. 第一个64第5位故障.
16 establish the interrupt vector table ud by 8259. Second channel timer test ends; 8254, first channel timer is nearing completion of testing. First 64, sixth bit faults.
17 adjust the video input / output, if equipped with video BIOS is enabled. First channel timer test ends; 8254, zeroth channel timer is nearing completion of testing. First 64, venth bit faults.
18 test video memory, if installed, lect the video BIOS pasd by, and can be bypasd. The zeroth channel timer test is over; the memory is about to start updating. First 64, eighth bit faults.
19 test first channel interrupt controller (8259) mask bit. Memory has been started, and memory updates will be completed. First 64, Ninth bit faults.
1A tests cond channel interrupt controllers (8259) mask bits.
Triggering the memory update line is about to check the 15 microcond pass / break time. First 64, tenth bit faults.
1B test CMOS battery level. Complete memory update time 30 microconds test; begin basic 64K memory test. First 64, eleventh bit faults.
1C test CMOS check sum. First, 64, Twelfth bit faults.
1D tting CMOS configuration. First, 64, thirteenth bit faults.
1E determines the size of the system memory and compares it to the CMOS value. First, 64, fourteenth bit faults.
1F test 64K memory to maximum 640K. First, 64, Fifteenth bit faults.
20 fixed 8259 ction measurement. Begin the basic 64K memory test; test the address line. The slave DMA register test is running or malfunctioning.
21 maintain an optional interrupt (NMI) bit (parity or check of the input / output channel). Test by address wire; is about to trigger parity. The main DMA register test is running or malfunctioning.
悯农的作者22 test 8259 interrupt function. Ending the triggering parity; beginning the rial data read / write test. The main interrupt mask register test is ongoing or malfunctioning.
23 test protection mode 8086 virtual mode and 8086 page mode. The basic 64K rial data read / write test is normal; any adjustment prior to the initialization of the interrupt vector. Dependent interrupt interrupt memory test is in progress or out of order.
24 measuring extended memory over 1MB. Any adjustment before the initialization of the vector is completed and the initial preparation of the interrupt vector is about to begin. Set the ES gment address register to the memory high end.
25 test all memory after the first 64K. Complete interrupt vector initial preparation. Start reading 8042 of the input / output ports for rotational interrupts. Load interrupt vector is in progress or malfunction.阴虱如何治疗
26 exceptions to the test protection mode. Read 8042 of the input / output port; begin to rotate the interrupt to start the global data as an initial preparation. Open the A20 address line; make it accessible.
27 determines the control or shielding of the cache memory RAM. All 1 data is ready for initial completion; then any initial preparation after the interrupt vector will be made. The keyboard controller test is ongoing or malfunctioning.
28 determines the cache control or the special 8042 keyboard controller. The initial preparation after the interrupt vector is completed; the monochrome mode is about to be t. CMOS power failure / check total calculation is in progress.
