单片机温度控制系统外文翻译外文文献英文文献中英翻译

更新时间:2023-07-15 03:43:44 阅读: 评论:0

Design of the Temperature Control System Bad on AT89C51
ABSTRACT
The principle and functions of the temperature control system bad on micro controller AT89C51 are studied, and the temperature measurement unit consists of the 1-Wire bus digital temperature nsor DS18B20. The system can be expected to detect the pret temperature, display time and save monitoring data. An alarm will be given by system if the temperature exceeds the upper and lower limit value of the temperature which can be t discretionarily and then automatic control is achieved, thus the temperature is achieved monitoring intelligently within a certain range. Basing on principle of the system, it is easy to make a variety of other non-linear control systems so long as the software design is reasonably changed. The system has been proved to be accurate, reliable and satisfied through field practice. KEYWORDS: AT89C51; micro controller; DS18B20; temperature
1 INTRODUCTION
Temperature is a very important parameter in human life. In the modern society, temperature control (TC) is not only ud in industrial production, but also widely ud in other fields. With the improvement of the life quality, we can find the TC appliance in hotels, factories and home as well. And the trend that
TC will better rve the whole society, so it is of great significance to measure and control the temperature. Bad on the AT89C51 and temperature nsor DS18B20, this system controls the condition temperature intelligently. The temperature can be t discretionarily within a certain range. The system can show the time on LCD, and save monitoring data; and automatically control the temperature when the condition temperature exceeds the upper and lower limit value. By doing so it is to keep the temperature unchanged. The system is of high anti-jamming, high control precision and flexible design; it also fits the rugged environment. It is mainly ud in people's life to improve the quality of the work and life. It is also versatile, so that it can be convenient to extend the u of the system. So the design is of profound importance. The general design, hardware design and software design of the system are covered.
1.1 Introduction
The 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output operations. MCS 51 microcontrollers are typically
ud for high-speed event control systems. Commercial applications include modems, motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instrument
s. The automotive industry u MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions t, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Becau of the critical applications, the market requires a reliable cost-effective controller with a low interrupt latency respon, ability to rvice the high number of time and event driven integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission critical applications such as an autopilot or anti-lock braking system, mistakes are financially prohibitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components is extremely expensive, as the devices are typically aled in modules with a total value veral times that of the component. To mitigate the problems, it is esntial that comprehensive testing of the controllers be carried out at both the component level and system level under worst ca environmental and voltage conditions. This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mis
sion successfully. Intel Chandler Platform Engineering group provides post silicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts. The type of the device and its application requirements determine which types of testing are performed on the device.
1.2 The AT89C51 provides the following standard features
4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture, a full duple r-ial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software lectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, rial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the
RAM contents but freezes the oscil–lator disabling all other chip functions until the next hardware ret.
1.3Pin Description0是不是正数
VCC Supply voltage.
GND Ground.
Port 0:Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be ud as high impedance inputs. Port 0 may also be configured to be the multiplexed low order address/data bus during access to external program and data memory. In this mode P0 has internal pull ups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull ups are required during program verification.
Port 1:Port 1 is an 8-bit bi-directional I/O port with internal pull ups. The Port 1 output buffers can sink/so -urce four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull ups and can be ud as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) becau of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and verification.
大闸蟹养殖Port 2:Port 2 is an 8-bit bi-directional I/O port with internal pull ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull ups and can be ud as inputs. As inputs, Port 2 pins that are externally being pulled low will so
抗日特种兵urce current (IIL) becau of the internal pull ups. Port 2 emits the high-order address byte during fetches from external program memory and during access to Port 2 pins that are externally being pulled low will source current (IIL) becau of the internal pull ups. Port 2 emits the high-order address byte during fetches from external program memory and during access to external data memory that u 16-bit address (MOVX@DPTR). In this application, it us strong internal pull-ups when emitting 1s. During access to external data memory that u 8-bit address (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals durin Flash programming and verification.
Port 3:Port 3 is an 8-bit bi-directional I/O port with internal pull ups. The Port 3 output buffers can sink/sou -rce four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull ups and can be ud as inputs. As inputs, Port
3 pins that are externally being pulled low will source current (IIL) becau of the pull ups.
Port 3 also rves the functions of various special features of the AT89C51 as listed below:
监控摄像头哪个品牌的好RST:Ret input. A high on this pin for two machine cycles while the oscillator is running rets the device.
昆明盘龙ALE/PROG:Address Latch Enable output pul for latching the low byte of the address during access to external memory. This pin is also the program pul input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be ud for external timing or clocking purpos. Note, however, that one ALE pul is skipped duri-ng each access to external Data Memory. If desired, ALE operation can be disabled by tting bit 0 of SFR location 8EH. With the bit t, ALE is active only during a MOVX or MOVC instruction. Otherwi, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
PSEN:Program Store Enable is the read strobe to external program memory. When theAT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.
EA/VPP:External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on ret. EA should be strapped to VCC for internal program executions. This pin alsreceives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.三只鸟
XTAL1:Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2 :Output from the inverting oscillator amplifier. Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for u as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be ud. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be obrved. Idle Mode In idle mode, the CPU puts itlf to sleep while all the on chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware ret. It should be noted that when idle is terminated by a hard ware ret, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal ret algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by ret, the instruction following the one that i
nvokes Idle should not be one that writes to a port pin or to external memory.
Power-down Mode
In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware ret. Ret redefines the SFRS but does not change the on-chip RAM. The ret should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. The AT89C51 code memory array is programmed byte-by byte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erad using the Chip Era Mode.
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关于阅读2 Programming Algorithm
Before programming the AT89C51, the address, data and control signals should be t up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Rai EA/VPP t
o 12V for the high-voltage programming mode. 5. Pul ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is lf-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object reached. Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written

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