3D TSV IC Processing 3D IC Technology Forum, SEMICON Taiwan 2010
Sesh Ramaswami
Sr. Director, Strategy Silicon Systems Group TSV Program
September 9th, 2010林保坚尼
SEMI大半导体产业网www.mi
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Outline Development Framework
Process Flows –Via Middle, Via Last and Interpor Technology readiness Summary
官僚
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Approach Flexible equipment and process architecture for Via Middle, Via Last, Backside contact and Interpor.
Leverage products to reduce capital investment.
–Foundry: Leverage damascene infrastructure.–Packaging: Leverage bump and RDL infrastructure.–Cost modeling and process integration approach from day 1.
Product readiness for customer technology development 1H 2010. Collaborate across industry eco-system:
–WSS (bonding, adhesives, de-bonding and cleans)–Non-WSS alternatives
–Thinning, defects, cleans and stress relief –Metrology (IR, X-Ray, acoustic) –R&D vs. prodn.–Consortia –IMEC, ITRI
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Silicon Interpor
Silvia ™Etch
Charger™PVD
哑铃平板卧推
960mRDL/ UBM
Producer Avila ™CVD
CVD cap over RDL
《竹石》
Raider ™ECD
RDL UBM
TSV
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5财神简笔画
ECD
Thermal stability Small overburden
CMP
Accurate end point and profile control
Products co-characterized under an end-to-end process framework
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5
PVD
Step coverage Thermal budget
Diffusion barrier (Ta vs. Ti)
CVD
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Reflexion LK
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淡妆怎么化Silvia
InVia Avila
桃仁的功效Etch Rate
Selectivity
Charger Endura
Raider
