AZV99
PECL/LVDS Oscillator Gain Stage & Buffer with Selectable Enable
FEATURES
• Green and RoHS Compliant /
Lead (Pb) Free Packages Available
• Similar Operation as AZ100LVEL16VT except with LVDS Outputs
• Operating Range of 3.0V to 5.5V • Minimizes External Components • Selectable Enable Polarity and Threshold (CMOS/TTL or PECL) • Available in a 2x2 or 3x3mm MLP Package
• S–Parameter (.s2p) and IBIS Model Files Available on Arizona Microtek Website
DESCRIPTION
The AZV99 is a specialized oscillator gain stage with LVDS output buffer including an enable. The enable input (EN) allows continuous oscillator operation by only controlling the Q HG /Q ¯HG outputs.
The AZV99 also provides a V BB and 470Ω internal bias resistors from D to V BB and D
¯ to V BB . The V BB pin can support 1.5 mA sink/source current. Bypassing V BB to ground with a 0.01 μF capacitor is recommended.
MLP 16, 3x3 mm Package (L) or DIE (X)
The MLP 16 and die versions of the AZV99 provide a lectable enable (EN). Enable polarity and threshold can be lected to accommodate either CMOS/TTL or PECL input levels. See the enable truth table for enable function. If enable pull-up is desired in the CMOS/TTL mode, an external ≤20k Ω resistor connecting EN to V CC will override the on-chip pull-down resistor.
Outputs Q/Q ¯ each have a lectable on-chip pull-down current source. See the current source truth table for current source functions. External resistors may also be ud to increa pull-down current to a maximum of 25mA (includes internal on-chip current source). PACKAGE AVAILABILITY
PACKAGE PART NUMBER MARKING NOTES
MLP 8 (2x2x0.75) Green / RoHS
Compliant / Lead (Pb) Free
AZV99NG V1G
<Date Code> 1,2 MLP 8 (2x2x0.75)
AZV99NA
V9
<Date Code>
1,2
MLP 8 (2x2x0.75)
Green / RoHS
Compliant / Lead (Pb) Free
AZV99NBG V8G <Date Code> 1,2
MLP 8 (2x2x0.75) Green / RoHS Compliant / Lead (Pb)
Free
AZV99NDG V2G
<Date Code> 1,2
MLP 16 (3x3) Green / RoHS Compliant / Lead (Pb) Free AZV99LG AZMG
V99
<Date Code> 1,2 TSSOP 8 RoHS
Compliant / Lead (Pb) Free
AZV99T+
AZ+
V99
1,2,3 DIE AZV99XP N/A 4
1
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape &
Reel. 2 Date code format: “Y” for year followed by “WW” for week. 3 Date Code “YWW” on underside of part. 4 Waffle Pack
MLP 8, 2x2 mm Package, NA, NB & ND Options
The MLP 8 NA, NB and ND options of the AZV99 provide a PECL/ECL level enable input (EN ¯¯¯). When the EN ¯¯¯ input is LOW, the Q ¯ and Q HG /Q ¯HG outputs pass data from the inputs. When EN ¯¯¯ is HIGH, the Q ¯ output continues to pass data while the Q HG output is forced high and the Q ¯HG output is forced low.
情弓
Only the Q ¯ output operates with a current source (4 mA) to V EE . This is accomplished by internal bonding of CS-SEL. An external resistor may also be ud to increa pull-down current to a maximum of 25mA (includes 4mA on-chip current source).
The AZV99NB and AZV99ND versions operates with a single ended data input (D). The D ¯ input is internally bonded directly to the V BB pin bypassing the 470Ω bias resistor.
TSSOP 8 Package (T), MLP 8 Package, (N)
The TSSOP 8 (T) and MLP 8 (N) versions of the AZV99 provide a CMOS/TTL level enable input (EN). When the EN input is HIGH, the Q ¯ and Q HG /Q ¯HG outputs pass data from the inputs. When EN is LOW, the Q ¯ output continues to pass data while the Q HG output is forced high and the Q ¯HG output is forced low.
Only the Q ¯ output operates with a current source (4 mA) to V EE . This is accomplished by internal bonding of CS-SEL. An external resistor may also be ud to increa pull-down current to a maximum of 25mA (includes 4mA on-chip current source).
The TSSOP 8 (T) and MLP 8 (N) AZV99 operates with a single ended data input (D). The D ¯ input is internally bonded directly to the V BB pin bypassing the 470Ω bias resistor.
个人信托
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
ENABLE TRUTH TABLE
Q D V BB EN/EN V EE EN-SEL
CS-SEL Q HG Q D Q HG
EN-SEL EN/EN ¯¯¯ Q/Q ¯ Q HG Q ¯HG NC NC PECL Low or NC PECL High or V CC Data Data Data High Data Low V EE 1
V EE 1 CMOS/TTL Low, V EE or NC CMOS/TTL High or V CC 2 Data Data High Data Low
Data EN-SEL connections must be less than 1Ω. 2 An external ≤20k Ω pull-up resistor between EN and V CC ensures a High when the EN pin is not driven. CURRENT SOURCE TRUTH TABLE
CS-SEL Q Q ¯ NC V EE 1 V CC 1
4mA typ. 8mA typ. 0 4mA typ.
8mA typ.
4mA typ. 1
CS-SEL connections must be less than 1Ω.
PIN DESCRIPTION
PIN FUNCTION
D/D ¯ Data Inputs Q/Q ¯ PECL Data Outputs
Q HG /Q ¯HG LVDS Data Outputs V BB Reference Voltage Output EN-SEL Selects Enable Logic EN/EN ¯¯ Enable Input
CS-SEL Selects Q and Q ¯ Current Source Magnitude V EE Negative Supply V CC Positive Supply
Absolute Maximum Ratings are tho values beyond which device life may be impaired.
Symbol Characteristic Rating Unit V CC Power Supply 0 to +6.0 Vdc
形容食物美味的词语
V I Input Voltage 0 to +6.0 Vdc
四十的英语怎么读V D/D¯ D/D¯ Input Voltage ±0.75 with respect to V BB Vdc
I OUT Output Current — Continuous Q/Q¯
—
Surge
Q/Q¯
—
Continuous
Q HG/Q¯HG
—
Surge
Q HG/Q¯HG
25
50
5
10
mA
T A Operating Temperature Range -40 to +85 °C
T STG Storage Temperature Range -65 to +150 °C
100K LVPECL DC Characteristics (V EE = GND, V CC = +3.3V)
-40°C 0°C 25°C 85°C
Symbol Characteristic
Min Max Min Max Min Max Min Max
Unit
V OH Output
HIGH
Voltage1,2Q/Q¯ 2255 2465 2275 2465 2275 2465 2275 2465 mV V OL Output LOW Voltage1,2 Q/Q¯ 1375 1745 1400 1680 1400 1680 1400 1680 mV
V IH Input HIGH Voltage
D/D¯1, EN (EN-SEL open)1
EN (EN-SEL tied to V EE)
2135
2000
2560
V CC
2135
2000
2560
V CC
2135
2000
2560
V CC
2135
2000
2560
V CC
mV
V IL Input LOW Voltage
D/D¯1, EN (EN-SEL open)1
EN (EN-SEL tied to V EE)
1400
GND
1825
800
1400
GND
1825
800
1400
GND
1825
800
1400
GND
1825
800
mV
V BB Reference
Voltage11910 2050 1910 2050 1910 2050 1910 2050 mV
I IL Input LOW Current EN3 0.5 0.5 0.5 0.5 μA
I IH Input HIGH Current EN3 150 150 150 150
μA
I EE Power Supply Current2 48 48 48 52
mA
CC
2.Specified with CS-SEL open.
3.Specified with EN-SEL open.
100K PECL DC Characteristics (V EE = GND, V CC = +5.0V)
-40°C 0°C 25°C 85°C
Symbol Characteristic
Min Max Min Max Min Max Min Max
Unit
V OH Output
HIGH
Voltage1,2 Q/Q¯ 3955 4165 3975 4165 3975 4165 3975 4165 mV
V OL Output LOW Voltage1,2 Q/Q¯ 3075 3445 3100 3380 3100 3380 3100 3380 mV
V IH Input HIGH Voltage
D/D¯1, EN (EN-SEL open)1
EN (EN-SEL tied to V EE)
3835
2000
4260
V CC
3835
2000
4260
V CC
孕妇梦见大海3835
2000
4260
V CC
3835
2000
4260
V CC
mV
V IL Input LOW Voltage
D/D¯1, EN (EN-SEL open)1
EN (EN-SEL tied to V EE)
3100
GND
3525
800
3100
GND
3525
800
3100
GND
3525
800
3100
GND
3525
800
mV
V BB Reference
Voltage13610 3750 3610 3750 3610 3750 3610 3750 mV
I IL Input LOW Current EN3 0.5 0.5 0.5 0.5 μA
I IH Input HIGH Current EN3 150 150 150 150
μA
I EE Power Supply Current2 48 48 48 52
mA
1.Voltage levels vary 1:1 with V CC.
2.Specified with CS-SEL open.
3.Specified with EN-SEL open.
LVDS DC Characteristics for Q HG/Q¯HG Outputs1(V EE = GND, V CC = +3.0V to +5.5V)
-40°C 0°C 25°C 85°C
必修二语文
Symbol Characteristic
Min Max Min Max Min Max Min Max
Unit
V OH Output
HIGH
Voltage 1600 1600 1600 1600
mV V OL Output
LOW
Voltage 900 900 900 900 mV V OC Output Common Mode Voltage21125 1375 1125 1375 1125 1375 1125 1375 mV
ΔV OC Change in Common Mode Voltage3-50 50 -50 50 -50 50 -50 50 mV
V OUT Single-Ended
Output
Swing 250 450 250 450 250 450 250 450 mV V DIFF_OUT Differential Output Swing500 900 500 900 500 900 500 900 mV
1. Specified with 100Ω resistor connecting Q HG and Q¯HG together.
2. Common mode voltage is the center voltage between Q HG and Q¯HG during a steady state.
3. Change in common mode voltage is the difference between common mode voltages at opposite binary states.
AC Characteristics (V EE = GND, V CC = +3.0V to +5.5V)
-40°C0°C25°C85°C
Symbol Characteristic
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Unit
t PLH / t PHL Propagation Delay
D to Q/Q¯ Outputs1 (SE)
D to Q HG/Q¯HG Outputs2 (SE)
400
550
400
550
400
550
430
630
ps
t SKEW Duty Cycle Skew Q/Q¯3(SE) 5 20 5 20 5 20 5 20 ps V PP (AC) Differnetial Input Swing480 1000 80 1000 80 1000 80 1000
mV
t r / t f Output Ri/Fall Times
(20% - 80%) Q/Q¯1
Q HG/Q¯HG2
100
180
260
280
100
180
260
280
100
180
260
280
100
180
260
280
ps
1. Specified with CS-SEL connected to V EE and Q/Q¯ with AC coupled 50Ω loads.
2. Specified with 100Ω resistor connecting Q HG and Q¯HG together.
武警特种警察学院
3. Duty cycle skew is the difference between a t PLH and t PHL propagation delay through a device.
4. The peak-to-peak differential input swing is the range for which AC parameters guaranteed. V D and V D¯ must remain within the range of ±750 mV
with respect to V BB.
S11, D to Q ¯, 50 Ω AC load on Q ¯
S12, D to Q ¯, 50 Ω AC load on Q ¯
0.7
0.750.80.850.90.95
50
150
250
350
450
550
650
750
850
950
1050
1150
1250
1350
Frequency (MHz)
M a g n i t u d e
P h a s e
00.0050.010.0150.020.025
50
150
250
350
450
550
650
750
850
950
1050115012501350
Frequency (MHz)
M a g n i t u d e
0.00
50.00
100.00
150.00
200.00
250.00
P h a s e
S21, D to Q ¯, 50 Ω AC load on Q ¯
S22, D to Q ¯, 50 Ω AC load on Q ¯
051015202530354050
150
250
350
450
550
650
750
850
950
1050
1150
1250
1350
Frequency (MHz)
M a g n i t u d e
20
40
60
80
100
120
140
160
180
海啸来袭P h a s e
0.4
0.50.60.70.850
150
250
350
450
550
650
750
850
950
1050
1150
1250
1350
Frequency (MHz)
M a g n i t u d e
100.00
120.00
140.00
160.00
180.00
P h a s e
