MC14536B
Programmable Timer
The MC14536B programmable timer is a 24−stage binary ripple counter with 16 stages lectable by a binary code. Provisions for an on−chip RC oscillator or an external clock are provided. An on−chip monostable circuit incorporating a pul−type output has been included. By lecting the appropriate counter stage in conjunction with the appropriate input clock frequency, a variety of timing can be achieved.
Features
•24 Flip−Flop Stages − Will Count From 20 to 224•Last 16 Stages Selectable By Four−Bit Select Code •8−Bypass Input Allows Bypassing of First Eight Stages •Set and Ret Inputs
•Clock Inhibit and Oscillator Inhibit Inputs •On−Chip RC Oscillator Provisions
•On−Chip Monostable Output Provisions
•Clock Conditioning Circuit Permits Operation with Very Long Ri and Fall Times
•Test Mode Allows Fast Test Sequence
•Supply V oltage Range = 3.0 Vdc to 18 Vdc
•Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load over the Rated Temperature Range •
Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to V SS )
Rating
Symbol Value Unit DC Supply Voltage Range V DD −0.5 to +18.0V Input or Output Voltage Range (DC or Transient)V in ,V out −0.5 to V DD
+ 0.5
V Input or Output Current (DC or Transient) per Pin
I in , I out ±10mA Power Dissipation per Package (Note 1)P D 500mW Ambient Temperature Range T A −55 to +125°C Storage Temperature Range
T stg −65 to +150
°C Lead T emperature, (8−Second Soldering)
T L
260
°C
Stress exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stress above the Recommended Operating Conditions may affect device reliability.1.Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C from 65_C to 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, V in and V out should be constrained to the range V SS v (V in or V out ) v V DD .
Unud inputs must always be tied to an appropriate logic voltage level (e.g., either V SS or V DD ). Unud outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, plea
download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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See detailed ordering and shipping information in the package dimensions ction on page 12 of this data sheet.
ORDERING INFORMATION
IN 1
Figure 1. Pin Assignment
Figure 2. Block Diagram
D DECOD
E OSC INH MONO−IN V DD A
B C OUT 1IN 1RESET SET V SS
CLOCK INH
8−BYPASS OUT 2FUNCTION TABLE
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS)
Characteristic Symbol V DD
Vdc
− 55_C25_C125_C石膏线效果图
雪研Unit Min Max Min
Typ
(Note 2)Max Min Max
Output Voltage“0” Level V in = V DD or 0V OL 5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
“1” Level V in = 0 or V DD V OH 5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Input Voltage“0” Level (V O = 4.5 or 0.5 Vdc)
(V O = 9.0 or 1.0 Vdc)
(V O = 13.5 or 1.5 Vdc)V IL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
空气质量日报
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
Vdc
“1” Level (V O = 0.5 or 4.5 Vdc)
(V O = 1.0 or 9.0 Vdc)
(V O = 1.5 or 13.5 Vdc)V IH
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
Vdc
Output Drive Current
(V OH = 2.5 Vdc)Source (V OH = 4.6 Vdc)Pins 4 & 5 (V OH = 9.5 Vdc)
(V OH = 13.5 Vdc)I OH
5.0
5.0
10
15
– 1.2
– 0.25
– 0.62
– 1.8
−
−
−
−
– 1.0
– 0.25
– 0.5
– 1.5
– 1.7
– 0.36
– 0.9
– 3.5
−
−
−
−
– 0.7
– 0.14
– 0.35
– 1.1
−
−
−
−
mAdc
(V OH = 2.5 Vdc)Source (V OH = 4.6 Vdc)Pin 13 (V OH = 9.5 Vdc)
(V OH = 13.5 Vdc)5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
−
−
−
−
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
−
−
−
−
– 1.7
– 0.36
– 0.9
– 2.4
−
−
−
−
mAdc
(V OL = 0.4 Vdc)Sink (V OL = 0.5 Vdc)
(V OL = 1.5 Vdc)I OL 5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
Input Current I in15−±0.1−±0.00001±0.1−±1.0m Adc Input Capacitance
(V in = 0)
C in−−−− 5.07.5−−pF
Quiescent Current (Per Package)I DD 5.0
10
15−
−
−
5.0
10
20
−
−
−
0.010
0.020
0.030
5.0
10
20
−
−
−
150
300
600
m Adc
Total Supply Current (Note3,4) (Dynamic plus Quiescent,
Per Package)
(C L = 50 pF on all outputs, all buffers switching)I T 5.0
10
15
I T = (1.50 m A/kHz) f + I DD
I T = (2.30 m A/kHz) f + I DD
I T = (3.55 m A/kHz) f + I DD
m Adc
2.Data labelled “Typ” is not to be ud for design purpos but is intended as an indication of the IC’s potential performance.
3.The formulas given are for the typical characteristics only at 25_C.
4.To calculate total supply current at loads other than 50 pF:
I T(C L) = I T(50 pF) + (C L – 50) Vfk
where: I T is in m A (per package), C L in pF, V = (V DD – V SS) in volts, f in kHz is input frequency, and k = 0.003.
SWITCHING CHARACTERISTICS (Note 5)(C L = 50 pF, T A= 25_C)
Characteristic Symbol V DD Min Typ (Note 6)Max Unit
Output Ri and Fall Time (Pin 13) t TLH, t THL = (1.5 ns/pF) C L + 25 ns
t TLH, t THL = (0.75 ns/pF) C L + 12.5 ns t TLH, t THL = (0.55 ns/pF) C L + 9.5 ns t TLH,
t THL 5.0
10
15
−
−
−
100
兔子喂什么
50
40
200
100
80
ns
Propagation Delay Time
Clock to Q1, 8−Bypass (Pin 6) High
t PLH, t PHL = (1.7 ns/pF) C L + 1715 ns t PLH, t PHL = (0.66 ns/pF) C L + 617 ns t PLH, t PHL = (0.5 ns/pF) C L + 425 ns t PLH,
t PHL
5.0
10
15
−
−
−
1800
650
450
3600
1300
1000
ns
Clock to Q1, 8−Bypass (Pin 6) Low
t PLH, t PHL = (1.7 ns/pF) C L + 3715 ns t PLH, t PHL = (0.66 ns/pF) C L + 1467 ns t PLH, t PHL = (0.5 ns/pF) C L + 1075 ns t PLH,
t PHL 5.0
10
15
−
−
−
3.8憎恨的反义词
第一颗卫星1.5
1.1
7.6
3.0
2.3
m s
Clock to Q16
t PHL, t PLH = (1.7 ns/pF) C L + 6915 ns t PHL, t PLH = (0.66 ns/pF) C L + 2967 ns t PHL, t PLH = (0.5 ns/pF) C L + 2175 ns t PLH,
t PHL 5.0
10
15
−
−
−
7.0
3.0
2.2
14
6.0
4.5
m s
Ret to Q n
t PHL = (1.7 ns/pF) C L + 1415 ns t PHL = (0.66 ns/pF) C L + 567 ns t PHL = (0.5 ns/pF) C L + 425 ns t PHL
5.0
10
15
−
−
−
1500
600
450
3000
1200
900
ns
Clock Pul Width t WH 5.0
10
15600
200
170
300
100
85
−
−
−
ns
Clock Pul Frequency (50% Duty Cycle)f cl 5.0
10
15−
−
−
1.2
3.0
5.0
0.4
1.5
2.0
MHz
Clock Ri and Fall Time t TLH,
t THL 5.0
10
15
No Limit
−
Ret Pul Width t WH 5.0
10
151000
400
300
500
200
150
−
六开头的四字成语−
−
ns
5.The formulas given are for the typical characteristics only at 25_C.
6.Data labelled “Typ” is not to be ud for design purpos but is intended as an indication of the IC’s potential performance.
PIN DESCRIPTIONS
INPUTS
SET (Pin 1) −A high on Set asynchronously forces Decode Out to a high level. This is accomplished by tting an output conditioning latch to a high level while at the same time retting the 24 flip−flop stages. After Set goes low (inactive), the occurrence of the first negative clock transition on IN1 caus Decode Out to go low. The counter’s flip−flop stages begin counting on the cond negative clock transition of IN1. When Set is high, the on−chip RC oscillator is disabled. This allows for very low−power standby operation.
RESET (Pin 2) −A high on Ret asynchronously forces Decode Out to a low level; all 24 flip−flop stages are also ret to a low level. Like the Set input, Ret disables the on−chip RC oscillator for s
tandby operation.
IN1 (Pin 3) −The device’s internal counters advance on the negative−going edge of this input. IN1 may be ud as an external clock input or ud in conjunction with OUT1 and OUT2 to form an RC oscillator. When an external clock is ud, both OUT1 and OUT2 may be left unconnected or ud to drive 1 LSTTL or veral CMOS loads.
8−BYPASS (Pin 6) −A high on this input caus the first 8 flip−flop stages to be bypasd. This device esntially becomes a 16−stage counter with all 16 stages lectable. Selection is accomplished by the A, B, C, and D inputs. (See the truth tables.)
CLOCK INHIBIT (Pin 7) −A high on this input disconnects the first counter stage from the clocking source. This holds the prent count and inhibits further counting. However, the clocking source may continue to run. Therefore, when Clock Inhibit is brought low, no oscillator startup time is required. When Clock Inhibit is low, the counter will start counting on the occurrence of the first negative edge of the clocking source at IN1.
OSC INHIBIT (Pin 14) −A high level on this pin stops the RC oscillator which allows for very low−power standby operation. May also be ud, in conjunction with an external clock, with esntial
ly the same results as the Clock Inhibit input.
MONO−IN (Pin 15) −Ud as the timing pin for the on−chip monostable multivibrator. If the Mono−In input is connected to V SS, the monostable circuit is disabled, and Decode Out is directly connected to the lected Q output. The monostable circuit is enabled if a resistor is connected between Mono−In and V DD. This resistor and the device’s internal capacitance will determine the minimum output pul widths. With the addition of an external capacitor to V SS, the pul width range may be extended. For reliable operation the resistor value should be limited to the range of
5 k W to 100 k W and the capacitor value should be limited to
a maximum of 1000 pf. (See figures 5, 6, 7, and 12).
A, B, C, D (Pins 9, 10, 11, 12) −The inputs lect the flip−flop stage to be connected to Decode Out. (See the truth tables.)
OUTPUTS
OUT1, OUT2 (Pin 4, 5) −Outputs ud in conjunction with IN1 to form an RC oscillator. The outputs are buffered and may be ud for 20 frequency division of an external clock. DECODE OUT
(Pin 13) −Output function depends on configuration. When the monostable circuit is disabled, this output is a 50% duty cycle square wave during free run. TEST MODE
The test mode configuration divides the 24 flip−flop stages into three 8−stage ctions to facilitate a fast test quence. The test mode is enabled when 8−Bypass, Set and Ret are at a high level. (See Figure 10.)
TRUTH TABLES
Input
Stage Selected
for Decode Out 8−Bypass D C B A
000009
0000110
0001011
0001112
0010013
0010114
0011015
0011116
0100017
0100118
0101019
0101120
0110021
0110122
0111023
0111124
Input
Stage Selected
for Decode Out 8−Bypass D C B A
100001
100012
100103
100114
101005
101016
无线局域网101107
101118
110009
1100110
1101011
1101112
1110013
1110114
1111015
1111116
LOGIC DIAGRAM
R E S E T
