Application Note
Order ID: AN_INAP_100
September 2008
Revision 1.3 APIX – Video Interface configuration
Abstract
APIX (A utomotive PIX el Link) is a high speed rial link for transferring Video/Audio data in Cameras and Dis-plays in Automotive Applications such as Infotainment and Driver Assistance systems. The link supports a downstream data rate of up to 1 Gbit/s. In addition, APIX features a full duplex, bidirectional sideband channel over the same or a parate link. This link can be ud to implement an independent control channel.
This application note describes in detail the configuration of the video interface of the INAP125T12/24 APIX transmitter and INAP125R12/24 APIX receiver devices.
System Architecture
The APIX Interface devices provide an uni-directional parallel TTL video interface and a bi-directional sideband interface (Figure 1). The rial interconnection between transmitter and receiver device compris a high speed differential down link and if required a lower speed differential up link. Array Figure 1: APIX parallel and rial interconnections
Alternatively the upstream link can also be established via common mode signaling on the down link twisted pair. This allows an implementation of the entire link with only two wires, however impacting the EMI robustness
of link, since the upstream sideband data is transferred as common mode signal.点铁成金
For automotive applications it is recommended to u the dedicated CML data link in upstream direction.
1.0 Video interface overview
The APIX link is designed for the direct connection of high resolution TFT displays and CMOS image nsors to central graphic and image processors, offering high speed transmission over a long distance with low EMI. The parallel video interface of the APIX devices can be configured individually to match all popular display and image nsor interfaces.
The link acts as transparent gateway for the parallel interface, in the following also called video or pixel inter-face, providing the data sampled at the interface at the transmitter at the same clock at the receiver. Due to this transparent characteristics, the interface may not only be ud for video data, it allows the transport of any data sampled at the interface pins.
The APIX video interface supports parallel RGB format with four different bit widths of 10,12,18 or 24 bit. In addition to the pixel data interfaces, three pixel control signals are implemented on the video interface. The video interface provides a pixel clock with programmable active edge (rising/falling) and programmable control signal polarity. The pixel interface width at the transmitter and receiver ha
s to be identical, to provide the correct function of the pixel interface.
The Video Data Interface operates in parallel to the Side-Band Data Interfaces, which offer downstream and upstream capabilities (e [2]).
The APIX high speed link operates independently of the pixel data speed or format. The video transport can be en as kind of conveyor belt, which is continously filled with data frames. The belt has a constant speed of 500MBit/s or 1GBit/s. The frames include video data, downstream sideband data and balancing overhead. In ca of lower pixel clock rates, the frames are filled with …dummy“ data, which are ignored at the receiver. Figure 1-2 illustrates the general conveyor belt functionality of the high speed data stream, including the over-head and sideband data.
Figure 1-2: APIX High Speed transport stream
2.0 APIX Clock Domains
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The APIX technology features a fundamental advantage to pixel clock driven devices by implementating a ded-icated clock system for the high speed rial link. With this, the rial link is not influenced by any variances or jitter at the pixel clock which lowers the risk for EMI issues. In addition, the link offers …hot-plug“ capabilities, as the high speed link synchronizes immediately on power up or connect and independently to video data.
The APIX transmitter features two parate clock domains for the video stream, which decouples the pixel clock of the link clock driving the high speed rial line. Video data consisting of parallel pixel data for color information and pixel control data for the framing of the image are registered in a video data buffer. The data buffer performs the clock domain crossing of the pixel clock domain and the system clock domain.
At the receiver, the link clock is recovered from the rial data stream and rves as reference for the main system clock. The recovered data are deframed and decoded and pushed into the receiver video data buffer. Finally, the data are provided at the pixel data interface, synchronous to the also recovered pixel clock. The following chapters discuss the different domains in more detail.
Plea e Figure 2-3 for an overview of the different clock domains in the complete APIX video data path.
Figure 2-3: Video Data path through APIX link
2.1 Pixel Clock Domain
The pixel clock at the transmitter needs to be provided by the main controller or graphics controller. Depending on the configuration of the transmitter interface (e [1]), the pixel data are sampled at the rising or the falling edge of the clock. The pixel data are sampled into a video data buffer and read out by the framing unit, which runs at the internal system clock. Therefore the video buffer acts as decoupling unit between the external pixel clock and the internal system clock.
The decoupling of the link clock and the pixel clock has veral advantages. It facilitates the implementation of multiple pixel data interfaces and guarantees a pixel clock independent link bandwidth which is the prerequisite for an efficient implementation of generic sideband data channels. Any variances or jitter do not affect the high speed rial link. It is moreover the basis for high performance and a low bit error rate of the physical layer. The pixel clock recovery unit at the receiver generates a pixel clock which, depending on the buffer status, dy-namically adapts the clock output. This dynamic handling avoids buffer under or overruns and also acts as de-jitter function for variances occuring at the pixel clock input at the transmitter. Plea e Section 5.0 for a detailed description of the dejitter function.
2.2 Link Clock Domain
The APIX link clock is derived from the transmitter system clock which is bad on the external crystal. At the transmitter, the system clock drives the framing and coding units and is ud to sample the video data from the video buffer. The system clock acts as basis for the high speed PLL, which generates the 500MHz or 1GHz clock for the rializer. Since the high speed clock is independent of the pixel clock, the signal quality of the high speed link is not affected by variances at the video interface.
The clock and data recovery unit (CDR) at the receiver regenerates the system clock, derived from the rial data stream. The system clock rves as main clock for the deframing and decoding of the data frames and is ud to push the data into the video data buffer.
2.3 AUX Clock domain (RX only)
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The receiver devices need to be supplied with an external crystal circuit, which is ud to generate the AUX clock domain. This clock only rves as reference for the CDR to recover data and system clock from the high speed rial link.
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3.0 Video interface configuration
The video interface of the APIX devices consists of the following data pins:
•PX_DATA[23:0]
•PX_CTRL[2:0]
•PX_CLK
It is recommended to consider ries resistors for all PX_DATA, PX_CTRL and PX_CLK input pins clo to the video source device to reduce the risk of data-related emissions and reflections.
3.1 Data width
逼仄The PX_DATA interface samples the parallel RGB data and can be configured to be driven in 10bit,
12bit, 18bit or 24bit mode. The configuration has to be stored as device configuration vector at address 02, bits [1:0] and gets active after ret.
Pixel control data like HSYNC, VSYNC and DATA ENABLE have to be connected to the PX_CTRL interface (plea e Section 3.3).
Configuration tting of address 02, bits [1:0]
•00: 10bit
•01: 12bit
•02: 18bit
•03: 24bit
In ca of a data with smaller than 24, it is recommended to pull the remaining pins to GND, e.g. for 18bit in-terface pins PX_DATA[23:17].
3.2 Pixel clock active edge
Pixel data are sampled (TX) or provided (RX) at pins PX_DATA[23:0] at either rising or falling edge of Pixel clock (PX_CLK). The lection of the falling or rising edge is done by the configuration vector. Configuration tting of address 2, bit 5
•0: falling edge
•1: rising edge鸡肉咖喱
The sampling edge is a local tting only and does not affect the remote device. For example, it is possible to sample in PX_DATA with rising edge at TX and eject the same data on the Rx side with falling edge and vice versa.
3.3 Pixel Control PX_CTRL
The PX_CTRL[2:0] signals are dedicated pins to carry the video control signals HSYNC, VSYNC and DATA ENABLE. The pins are sampled at PX_CLK and transmitted transparently to the receiver. However, DATA EN-ABLE is also ud by the APIX devices to align the data stream and to recognize the start of the pixel data. •PX_CTRL0: HSYNC
•PX_CTRL1: VSYNC
•PX_CTRL2: DATA ENABLE
The DATA ENABLE (DE) signal is mandatory for correct operation of the APIX link. DE needs to be enabled for a minimum of 4 pixel clocks for correct operation.
红叶菜>铜雀春深锁二乔上一句3.3.1 Transmitter
At the transmitter, a rising edge of DE indicates the start of a new t of data. In order to realign the data to the frame structure at the rial link, the rializer us a new empty frame at the rial link. The active frame is filled with …empty“ data. The APIX devices offer different operation modes (e Section 3.4) to configure the density of the DE signal for video streaming.
Figure 3-4 illustrates the gmentation of the pixel data to the 16 bit frame structure with the exampl
e of 18 bit data width and shows the impact of DE on the frame alignment of the transmitter. The example shows the trans-mission of 4 Pixels. Pixel 0 is nt together with a rising edge at DE and therefore forces a realignment at the rial link.
The figure is simplified as it doesn‘t consider different payload sizes of the frames for sideband data.
Figure 3-4: Segmentation of pixel data and alignment to DATA ENABLE
