64K x 32 Synchronous-Pipelined Cache RAM
CY7C1329
社区证明怎么开Features
•Supports 133-MHz bus for Pentium® and PowerPC™ operations with zero wait states
•Fully registered inputs and outputs for pipelined operation
•64K x 32 common I/O architecture •Single 3.3V power supply •Fast clock-to-output times —4.2 ns (for 133-MHz device)—5.5 ns (for 100-MHz device)—7.0 ns (for 75-MHz device
•Ur-lectable burst counter supporting Intel® Pentium interleaved or linear burst quences •Separate processor and controller address strobes •Synchronous lf-timed writes •Asynchronous output enable •JEDEC-standard 100 TQFP pinout
•“ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1329 is a 3.3V , 64K by 32 synchronous-pipelined cache SRAM designed to support zero wait state condary cache with minimal glue logic.
All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Max-imum access delay from the clock ri is 4.2 ns (133-MHz device).
The CY7C1329 supports either the interleaved burst -quence ud by the Intel Pentium processor or a linear burst quence ud by processors such as the PowerPC. The burst quence is lected through the MODE pin. Access can be initiated by asrting either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC) at clock ri.Address advancement through the burst quence is con-trolled by the ADV input. A 2-bit on-chip wraparound burst counter captures the first address in a burst quence and automatically increments the address for the rest of the burst access.
Byte write operations are qualified with the four Byte Write Select (BW [3:0]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous lf-timed write cir-cuitry.
广告设计图
Three synchronous Chip Selects (CE 1, CE 2, CE 3) and an asynchronous Output Enable (OE) provide for easy bank -lection and output three-state control. In order to provide prop-er data during depth expansion, OE is masked during the first clock of a read cycle when emerging from a delected state.
Intel and Pentium are registered trademarks of Intel Corporation.PowerPC is a trademark of IBM Corporation.
CLK ADV ADSC A [15:0]GW BWE BW 3BW 2BW 1
BW 0CE 1CE 3
CE 2OE ZZ
BURST COUNTER
DQ[31:24]BYTEWRITE REGISTERS
ADDRESS
REGISTER D
Q OUTPUT REGISTERS INPUT REGISTERS 64KX32MEMORY ARRAY
CLK
CLK
Q 0
Q 1Q
D C
E CE CLR
SLEEP CONTROL
DQ[23:16]BYTEWRITE REGISTERS D Q D Q DQ[15:8]
BYTEWRITE REGISTERS DQ[7:0]
BYTEWRITE REGISTERS
D
Q ENABLE REGISTER D Q CE CLK ENABLE DELAY REGISTER D Q CLK
3232
16
14
14
16(A [1:0])2
MODE ADSP Logic Block Diagram
DQ [31:0]
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Pin Configuration
A 5
A 4
A 3
A 2
A 1
A 0
N C N C V S S
V D D
N C N C A 10
A 11
A 12
A 13
A 14
A 15
N C NC DQ 15DQ 14V DDQ V SSQ DQ 13DQ 12DQ 11DQ 10V SSQ V DDQ DQ 9DQ 8V SS NC V DD ZZ DQ 7DQ 6V DDQ V SSQ DQ 5DQ 4DQ 3DQ 2V SSQ V DDQ DQ 1DQ 0NC
NC DQ 16DQ 17V DDQ V SSQ DQ 18DQ 19DQ 20DQ 21V SSQ V DDQ DQ 22DQ 23NC V DD NC V SS DQ 24DQ 25V DDQ V SSQ DQ 26DQ 27DQ 28DQ 29V SSQ V DDQ DQ 30DQ 31NC
A 6A 7C E 1
C E 2
B W 3
B W 2
B W 1
B W 0
C E 3
V D D
V S S
C L K G W B W E O E A
D S C A D S P A D V A 8
A 9
123456789101112131415161718192021222324252627282930
3132333435363738394041424344454647484950
80797877767574737271706968676665646362616059585756555453525110099989796959493929190898887868584838281
M O D E BYTE0
BYTE1
BYTE3小葱拌豆腐歇后语
BYTE2
100-Pin TQFP
CY7C1329
Selection Guide
7C1329-133
7C1329-100
7C1329-75
Maximum Access Time (ns) 4.2 5.57.0Maximum Operating Current (mA)Commercial 325310260Maximum CMOS Standby Current (mA)
Commercial
5
5
5
Pin Definitions
Pin Number Name I/O
Description
49–44, 81,82, 99, 100, 32–37A [15:0]Input-Synchronous Address Inputs ud to lect one of the 64K address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1, CE 2, and CE 3 are sampled active. A [1:0] feed the 2-bit counter.
96–93BW [3:0]Input-Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK.
88
GW
Input-Synchronous Global Write Enable Input, active LOW. When asrted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW [3:0] and BWE).
87BWE Input-Synchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asrted LOW to conduct a byte write.
1457年
89CLK Input-Clock Clock input. Ud to capture all synchronous inputs to the device. Also ud to increment the burst counter when ADV is asrted LOW, during a burst operation.98
CE 1Input-Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Ud in conjunction with CE 2 and CE 3 to lect/delect the device. ADSP is ignored if CE 1 is HIGH.
怎样种红薯97CE 2Input-Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Ud in conjunction with CE 1 and CE 3 to lect/delect the device.
92CE 3Input-Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Ud in conjunction with CE 1 and CE 2 to lect/delect the device.
86
OE
Input-Asynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasrted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a delected state.
83ADV Input-Synchronous
Advance Input signal, sampled on the rising edge of CLK. When asrted, it auto-matically increments the address in a burst cycle.
84
ADSP
Input-Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK. When asrt-ed LOW, A [15:0] is captured in the address registers. A [1:0] are also loaded into the burst counter. When ADSP and ADSC are both asrted, only ADSP is recognized. ASDP is ignored when CE 1 is deasrted HIGH.
85ADSC
Input-Synchronous Address Strobe from Controller, sampled on the rising edge of CLK. When asrt-ed LOW, A [15:0] is captured in the address registers. A [1:0] are also loaded into the burst counter. When ADSP and ADSC are both asrted, only ADSP is recognized.64ZZ
Input-Asynchronous
ZZ “sleep ” Input. This active HIGH input places the device in a non-time critical “sleep ” condition with data integrity prerved.
29, 28, 25–22, 19, 18,13,12, 9–6, 3, 2, 79, 78, 75–72, 69, 68, 63, 62 59–56, 53, 52
DQ [31:0]I/O-Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A [15:0] during the previous clock ri of the read cycle. The direction of the pins is controlled by OE. When OE is asrted LOW, the pins behave as outputs. When HIGH, DQ [31:0] are placed in a three-state condition.
15, 41, 65, 91V DD Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power supply.
17, 40, 67, 90V SS Ground Ground for the core of the device. Should be connected to ground of the system.4, 11, 20, 27, 54, 61, 70, 77V DDQ I/O Power Supply Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.5, 10, 21, 26, 55, 60, 71, 76V SSQ I/O Ground Ground for the I/O circuitry. Should be connected to ground of the system.31
MODE
Input-Static Selects burst order. When tied to GND lects linear burst quence. When tied to V DDQ or left floating lects interleaved burst quence. This is a strap pin and should remain static during device operation.1, 14, 16, 30, 38, 39, 42, 43, 50, 51, 66, 80
NC -
No Connects.
Introduction
Functional Overview
All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Max-imum access delay from the clock ri (t CO) is 4.2 ns (133-MHz device).
The CY7C1329 supports condary cache in systems utilizing either a linear or interleaved burst quence. The interleaved burst order supports Pentium and i486 processors. The linear burst quence is suited for processors that utilize a linear burst quence. The burst order is ur lectable, and is de-termined by sampling the MODE input. Access can be initi-ated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst quence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first ad-dress in a burst quence and automatically increments the address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[3:0]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchro-nous lf-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank -lection and output three-state control. ADSP is ignored if CE1 is HIGH.
Single Read Access
This access is initiated when the following conditions are sat-isfied at clock ri: (1) ADSP or ADSC is asrted LOW, (2) CE1, CE2, CE3 are all asrted active, and (3) the write signals (GW, BWE) are all deasrted HIGH. ADSP is ignored if CE1 is HIGH. The address prented to the address inputs (A[15:0]) is stored into the address advancement logic and the Address Register while being prented to the memory core. The cor-responding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 4.2 ns (133-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a delected state to a lected state, its outputs are always three-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Concutive single read cycles are supported. Once the SRAM is delected at clock ri by the chip lect and either ADSP or ADSC signals, its output will three-state immediately.
Single Write Access Initiated by ADSP
This access is initiated when both of the following conditions are satisfied at clock ri: (1) ADSP is asrted LOW, and (2) CE1, CE2, CE3 are all asrted active. The address prented to A[15:0] is loaded into the address register and the address advancement logic while being delivered to the RAM core. The write signals (GW, BWE, and BW0–BW3) and ADV inputs are ignored during this first cycle.
ADSP triggered write access require two clock cycles to complete. If GW is asrted LOW on the cond clock ri, the data prented to the DQ[31:0] inputs is written into the corre-sponding address location in the RAM core. If GW is HIGH, then the write operation is controlled by BWE and BW[3:0] sig-nals. The CY7C1329 provides byte write capability that is de-scribed in the Write Cycle Description table. Asrting the Byte Write Enable input (BWE) with the lected Byte Write (BW[3:0]) input will lectively write to only the desired bytes. Bytes not lected during a byte write operation will remain unaltered. A synchronous lf-timed write mechanism has been provided to simplify the write operations.
Becau the CY7C1329 is a common I/O device, the Output Enable (OE) must be deasrted HIGH before prenting data to the DQ[31:0] inputs. Doing so will three-state the output driv-ers. As a safety precaution, DQ[31:0] are automatically three-stated whenever a write cycle is detected, regar
dless of the state of OE.
Single Write Access Initiated by ADSC
ADSC write access are initiated when the following condi-tions are satisfied: (1) ADSC is asrted LOW, (2) ADSP is deasrted HIGH, (3) CE1, CE2, CE3 are all asrted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BW[3:0]) are asrted active to conduct a write to the desired byte(s). ADSC triggered write access require a single clock cycle to complete. The address prented to A[15:0] is loaded into the address register and the address ad-vancement logic while being delivered to the RAM core. The ADV input is ignored during this cycle. If a global write is con-ducted, the data prented to the DQ[31:0] is written into the corresponding address location in the RAM core. If a byte write is conducted, only the lected bytes are written. Bytes not lected during a byte write operation will remain unaltered. A Synchronous lf-timed write mechanism has been provided to simplify the write operations.
Becau the CY7C1329 is a common I/O device, the Output Enable (OE) must be deasrted HIGH before prenting data to the DQ[31:0] inputs. Doing so will three-state the output driv-ers. As a safety precaution, DQ[31:0] are automatically three-stated whenever a write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1329 provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst -quence. The interleaved burst quence is designed specifi-cally to support Intel Pentium applications. The linear burst quence is designed to support processors that follow a lin-ear burst quence. The burst quence is ur lectable through the MODE input.
Asrting ADV LOW at clock ri will automatically increment the burst counter to the next address in the burst quence. Both read and write burst operations are supported. Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]A[1:0]A[1:0]A[1:0] 00011011 01001110 10110001 11100100
Sleep Mode
The ZZ input pin is an asynchronous input. Asrting ZZ plac-es the SRAM in a power conrvation
“sleep ” mode. Two clock cycles are required to enter into or exit from this “sleep ” mode.While in this mode, data integrity is guaranteed. Access pending when entering the “sleep ” mode are not considered valid nor is the completion of the operation guaranteed. The device must be delected prior to entering the “sleep ” mode.CE 1, CE 2, CE 3, ADSP , and ADSC must remain inactive for the duration of t ZZREC after the ZZ input returns LOW.
Linear Burst Sequence
First Address Second Address Third Address Fourth Address A [1:0]A [1:0]A [1:0]A [1:0]00011011011011001011000111
00
01
10
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min
Max Unit I DDZZ
Snooze mode standby current ZZ > V DD − 0.2V 3mA t ZZS Device operation to
ZZ ZZ > V DD − 0.2V 2t CYC
ns t ZZREC
ZZ recovery time
ZZ < 0.2V
2t CYC ns
Cycle Descriptions [1,2,3]
Next Cycle Add. Ud ZZ CE 3CE 2CE 1ADSP ADSC ADV OE DQ Write Unlected None L X X 1X 0X X Hi-Z X Unlected None L 1X 00X X X Hi-Z X Unlected None L X 000X X X Hi-Z X Unlected None L 1X 010X X Hi-Z X Unlected None L X 0010X X Hi-Z X Begin
Read External L 0100X X X Hi-Z X Begin
Read External L 01010X X Hi-Z read Continue Read Next L X X X 1101Hi-Z read Continue Read Next L X X X 1100DQ read Continue Read Next L X X 1X 101Hi-Z read Continue Read Next L X X 1X 100DQ read Suspend Read Current L X X X 1111Hi-Z read Suspend Read Current L X X X 1110DQ read Suspend Read Current L X X 1X 111Hi-Z read Suspend Read Current L X X 1X 110DQ read Begin Write Current L X X X 111X Hi-Z write Begin Write Current L X X 1X 11X Hi-Z write Begin
Write External L 01010X X Hi-Z write Continue Write Next L X X X 110X Hi-Z write Continue Write Next L X X 1X 10X Hi-Z write Suspend Write Current L X X X 111X Hi-Z write Suspend Write Current L X X 1X 11X Hi-Z write ZZ “sleep ”
None
H
X
X
X
X
X
X
X
Hi-Z
X
Notes:
1.X=”Don't Care ”, 1=HIGH, 0=LOW.
2.Write is defined by BWE, BW [3:0], and GW. See Write Cycle Descriptions table.
3.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
Maximum Ratings
(Above which the uful life may be impaired. For ur guide-lines, not tested.)
Storage T emperature .....................................−65°C to +150°C Ambient T emperature with
Power Applied ..................................................−55°C to +125°C Supply Voltage on V DD Relative to GND .........−0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State [7].....................................−0.5V to V DDQ + 0.5V DC Input Voltage [7]..................................−0.5V to V DDQ + 0.5V
Current into Outputs (LOW).........................................20 mA Static >2001V (per MIL-STD-883, Method 3015)
>200 mA
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Notes:
4.X=”Don't Care ”, 1=Logic HIGH, 0=Logic LOW.
5.The SRAM always initiates a read cycle when ADSP asrted, regardless of the state of GW, BWE, or BW [3:0]. Writes may occur only on subquent clocks
after the ADSP or with the asrtion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a “don't care ” for the remainder of the write cycle.
6.OE is asynchronous and is not sampled with the clock ri. It is masked internally during write cycles. During a read cycle DQ=High-Z when OE is inactive or
when the device is delected, and DQ=data when OE is active.
7.Minimum voltage equals –2.0V for pul durations of less than 20 ns.8.T A is the ca temperature.
Write Cycle Descriptions [4,5,6]
Function
GW BWE BW 3BW 2BW 1BW 0Read 11X X X X Read
101111Write Byte 0 - DQ [7:0]101110Write Byte 1 - DQ [15:8]101101Write Bytes 1,
0101100Write Byte 2 - DQ [23:16]101011Write Bytes 2, 0101010Write Bytes 2, 1101001Write Bytes 2, 1,
01
01000Write Byte 3 - DQ [31:24]
1
00111Write Bytes 3, 01
00110Write Bytes 3,
1100101Write Bytes 3, 1, 0100100Write Bytes 3, 2100011Write Bytes 3, 2,
0100010Write Bytes 3, 2, 1100001Write All Bytes 100000Write All
Bytes 0
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X
X
X
X
Operating Range
Range Ambient Temperature [8]V DD V DDQ Com ’l
0°C to +70°C
3.3V −5%/+10%
3.3V −5%/+10%
