Pin Function 1Vd 2Vg 3
4RF Out
5678
RF In
top view
package ba: RF and DC GND
Vg 7
56RFin 8 4 RFout
Vd Description
Avago Technologies’ AMMP-6120 is an easy-to-u in-tegrated frequency multiplier (x2) in a surface mount package designed for commercial communication systems. The MMIC takes a 4 to 12 GHz input signal and doubles it to 8 to 24 GHz. It has integrated amplification, matching, harmonic suppression, and bias networks. The input/output are matched to 50 Ω and fully DC blocked. The MMIC is fabricated using PHEMT technology. The backside of the package is both RF and DC ground. This helps simplify the asmbly process and reduces asmbly related performance variati
ons and costs. The surface mount package allows elimination of “chip & wire” asmbly for lower cost. This MMIC is a cost effective alternative to hybrid (discrete-FET), passive, and diode doublers that require complex tuning and asmbly process.
Features
• 5x5mm Surface Mount Package • Frequency Range : 8-24 GHz output (Uable to 26 GHz)• Broad input power range: -11 to +5 dBm • Output Power : +16 to +18 dBm
• Harmonic Suppression : 20 dBc (Fundamental)• DC requirements : -1.4V and 5V, 112 mA @ Pin= +3dBm
Applications
• Microwave Radio systems • Satellite VSAT and DBS systems • 802.16 & 802.20 WiMax BWA systems • WLL and MMDS loops
AMMP-6120
8-24 GHz x2 Frequency Multiplier
Data Sheet
AMMP-6120 Absolute Maximum Ratings [1]
Note:
1. Operation in excess of any one of the conditions may result in permanent damage to this device.
Symbol Parameters/Conditions Unit Minimum
Maximum Vd Positive Drain Voltage V 7Vg Gate Supply Voltage V -3.0 +0.5Id Drain Current mA 120Pin CW Input Power dBm 15Tch Operating Channel Temp. °C +150Tstg Storage Ca Temp.
°C -65 +150Tmax各地
Maximum Asmbly Temp.(60 c. max.)
°C
+300
AMMP-6120 DC Specifications/Physical Properties [1]
萨尔浒RF Specifications (3,4) (T A =25°C, Vd=5V, Vg=-1.4V, Id (Q)=85mA, Zin=Zout=50Ω)
Notes:
3. Small/Large -signal data measured in a fully de-embedded test fixture form TA = 25°C.
4. Pre-asmbly into package performance verified 100% on-wafer.
斜渐近线5. This final package part performance is verified by a functional test correlated to actual performance at Fout=10GHz output, Pin=+3dBm.
6. All tested parameters guaranteed with measurement accuracy ±0.5dBm for Pout and ±3dBc for FS.
Notes:
1. Ambient operational temperature TA=25°C unless otherwi noted.
2. Channel-to-backside Thermal Resistance (T channel (Tc) = 34°C) as measured using infrared mic汽车报废补贴
roscopy. Thermal Resistance at backside tempera-ture (Tb) = 25°C calculated from measured data.
Symbol Parameters and Test Conditions
Units Typ.Maximum Id Drain Supply Current (under any RF power drive and temperature) (Vd=5V)mA 85110
Ig Gate Current
mA 9q ch-b
Thermal Resistance [2]
(Backside temperature, Tb = 25°C)
°C/W
34
Symbol Parameters and Test Conditions Units Minimum Typ.Pout Output Power [5]dBm 13导气管
16Rlin Input Return Loss dB -15RLout Output Return Loss
dB -10IP-1dB Input Power @ 1dB Gain Comp dBm 2Sup Fundamental Suppresion [5]dBc 1825Sup33rd Harmonic Suppression dBc 25Sup44th Harmonic Suppression
dBc
35
SSBPN
Single Side Band Pha Noi (@100kHz offt)
dBc Hz -140 (fout=15.6GHz)
AMMP-6120 Typical Performances
(T A = 25°C,Z in = Z out = 50 Ω, Vd=5V, Vg=-1.4V)
-30
-25-20-15-10-5
Output Frequency (GHz)
O u t p u t P o w e r (d B m )
1011121314151617
1819
什么时候上环最合适Output Frequency (GHz)
O u t p u t P o w e r [2H ] (d B m )
81012
14161820222426
Output Frequency [GHz]
S u p p r e s s i o n [1H ] (d B c )
Figure 3. Output Power [2H] vs. Output Freq. at variable Pin Figure 4. Fundamental Suppression at variable Pin
Figure 1. Output Power vs. Output Freq. @ Pin=+3dBm
Frequncy (GHz)
I /P & O /P R e t u r n L o s s (d B )
Input Power [1H] (dBm)
T o t a l D r a i n C u r r e n t [I d ] (m A )
Figure 6. Variation of total drain current with input power
-30
-25-20-15-10-5101520Output Frequency (GHz)
O u t p u t P o w e r (d B m )
Figure 2. Output Power vs. Output Freq. over temp @ Pin=+3dBm
Figure 5. Input and Output Return Loss
Input Power [1H] (dBm)
O u t p u t P o w e r [2H ] (d B m )
Input Power [1H] (dBm)
S u p p r e s s i o n [1H ] (d B c )
Figure 11. 2H Output Power Vs Input Power @ Fout=14GHz
Figure 12. Fundamental Supp. Vs Input Power @ Fout=14GHz
Input Power [1H] (dBm)
O u t p u t P o w e r [2H ] (d B m )
-11
-9-7
-5-3-11357911
Input Power [1H] (dBm)
S u p p r e s s i o n [1H ] (d B c )
Figure 9. 2H Output Power Vs Input Power @ Fout=10GHz Figure 10. Fundamental Supp. Vs Input Power @ Fout=10GHz
Input Power [1H] (dBm)
O u t p u t P o w e r [2H ] (d B m )
Input Power [1H] (dBm)
S u p p r e s s i o n [1H ] (d B c )
Figure 7. 2H Output Power Vs Input Power @ Fout=8GHz Figure 8. Fundamental Supp. Vs Input Power @ Fout=8GHz
-11
-9
-7
-5
-
3-11357911
Input Power [1H] (dBm)
O u t p u t P o w e r [2H ] (d B m )
Input Power [1H] (dBm)
S u p p r e s s i o n [1H ] (d B c )
Input Power [1H] (dBm)
O u t p u t P o w e r [2H ] (d B m )
Input Power [1H] (dBm)
O u t p u t P o w e r [2H ] (d B m )
Input Power [1H] (dBm)
S u p p r e s s i o n [1H ] (d B c )
Input Power [1H] (dBm)
S u p p r e s s i o n [1H ] (d B c )
Figure 15. 2H Output Power Vs Input Power @ Fout=20GHz Figure 17. 2H Output Power Vs Input Power @ Fout=22GHz Figure 14. Fundamental Supp. Vs Input Power @ Fout=16GHz
单克隆抗体药物
Figure 13. 2H Output Power Vs Input Power @ Fout=16GHz
Figure 16. Fundamental Supp. Vs Input Power @ Fout=20GHz
Figure 18. Fundamental Supp. Vs Input Power @ Fout=22GHz
Figure 22. Top Level Schematic of Frequency doubler
Figure.21 SSB Pha Noi of frequency doubler (Pin=+2dBm, fout=15.6GHz)
-170
-160-150-140-130-120-110-100
Offt Frequency [Hz]
S S B P h a s e N o i s e (d B c /H z )
Biasing and Operation
The frequency doubler MMIC consists of a balun. The outputs of this balun feed the gates of balanced FETs and the drains are connected to form the single-ended output. This results in fundamental frequency & odd harmonics cancellation. The even harmonic drain currents are in pha and thus add in pha. The input matching network (M/N) is designed to provide good match at fundamental frequencies and produces high impedance mismatch to higher harmonics.
The AMMP-6120 is biad with a single positive drain supply Vdd and a single negative gate supply using parate bypass capacitors. It is normally biad with the drain supply connected to Vd and the gate supply connected to Vg. For most applications it is recommended to u a Vg =-1.2V to -1.4V and Vd=4.5V to 5.0V.
The RF input and output ports are AC coupled thus no DC voltage is prent at either port. The ground connection is made via the package ba.”
The AMMP-6120 performance changes with Drain Voltage (Vd) and Gate bias (Vg) as shown in the previous graphs. Improvements in output power or fundamental suppres-sion performance are possible by optimizing the Vg from -1.2V to -1.4V and/or Vd from 4.5 to 5.0V.
A simplified schematic of the frequency multiplier is shown in figure 22. The active balun circuit and the output amplifier of the circuit are lf biad. The Vg negative bias (below pinch off) is only applied to FETs ‘F1’ and ‘F2’. FETs ‘F1’ and ‘F2’ have no significant contribution to total drain current therefore Vg cannot be ud to t drain current. It should only be ud to optimize the output power and fundamental & higher harmonics suppression of the doubler.
Refer to the Absolute Maximum Ratings table for allowed DC and thermal conditions.三线表格式
Figure. 19 2H Output Power Vs Input Power @ Fout=26GHz
Figure. 20 Fundamental Supp. Vs Input Power @ Fout=26GHz
2468101214161820
Input Power [1H] (dBm)
O u t p u t P o w e r [2H ] (d B m )
-11
-
9
-7
-5
-3-11357
9
11
Input Power [1H] (dBm)
S u p p r e s s i o n [1H ] (-d B c )
