ARM汇编语⾔⾯试题
1. What registers are ud to store the program counter and linker register?
A:r15 and r14 are ud to store the program counter and linker register, respectively.
2. What is r13 ofter ud to store?
A:r13 are often ud to store Stack Pointer
3. Which mode, or modes has the fewest available number of registers available? How many and why?
A: ARM has six operating modes, there are Ur、FIQ、IRQ、Supervisor、Abort and Undef.ARM Architecture version 4 also hasan operating mode called System. the modes of ur and system can access the least registers, they can only access 17 registers, including r0-r15 and CPSR. the two modes can not access SPSR.哺乳期食谱
4. Convert the _G_C_D algorithm given in this flowchart into 1）“normal”asmbler, where only branches can be conditional. 2) ARM asmbler,
where all instructions are conditional, thus improving code density.
低脂食物一览表
“Normal” Asmbler
mov r0, #27
mov r1, #9
g_c_dcmp r0, r1
beq stop
blt less ;if r0 < r1(lt表⽰带符号数⼩于)
sub r0, r0, r1
bal g_c_d ; al－always
lesssub r1, r1, r0
bal gcd
stop
ARM conditional asmbler
gcd cmp r0, r1
subgt r0, r0, r1
sublt r1, r1, r0
bne gcd
5. Specify instructions which will implement the following:
a) r0 = 16 b) r1 = r0 *4
wps首行缩进2字符怎么设置c) r0 = r1/16 d) r1 = r2 * 7
A: a) MOV r0, #16 b) MOV r1, r0, LSL #2
c) MOV r0, r1, ASR #4 d) RSBr1, r2, r2, LSL #3
1. What will the following instructions do?
统计表格怎么做
a) ADDS r0, r1, r1, LSL #2 b) RSB r2, r1, #0
A: a) r0 = r1 + r1 * 4 = r1 *5 and update the conditional flags
b) r2 = 0 – r1
2. What does the following instruction quence do?
ADD r0, r1, r1, LSL #1
SUBr0, r0, r1, LSL #4
ADD r0, r0, r1, LSL #7
A:r0 = r1 * 115 = r1 * (128 – 13) = r1 * (128 – 16 + 3) = r1 * 3- r1 * 16 + r1 * 128
8．rite a gment of code that add together elements x to x+(n-1) of an
array, where the element x = 0 is the first element of the array. Each element of the array is word size(ie. 32bits). The gment should u post-indexed addressing.At the start of your gment, you should assume that:
r0 points to the start of the array, r1 = x, r2 = n
A: ADD r0, r0, r1, LSL #2 ;t r0 to the address of element x
ADD r2, r0, r2, LSL #2 ;t r2 to the address of element x + n
MOV r1, #0 ;initialize the counter
loop
LDR r3, [r0], #4 ;access the element and mov to the next
ADD r1, r1, r3 ;add content to the counter
CMP r0, r2 ;reach element x+n?
BLT loop ;If not –repeat for next element风景句子
;on exit, sum contained in r1
9．The contents of registers r0 to r6 need to be swapped around thus:
王明欢
r0 moved into r3
r1 moved into r4
r2 moved into r6
r3 moved into r5
r4 moved into r0
r5 moved into r1
r6 moved into r2
Write a gment of code that u full descending stack operations to carry this out, and hence requires no u of any other registers for temporary storage.
A: STMFD sp!,{r0-r6}
悲伤的歌曲LTMFD sp!, {r3, r4, r6}
LTMFD sp!, {r5}
LTMFD sp!, {r0-r2}
许昌学院图书馆
10.Write a short code gment that performs a mode change by modifying the
contents of the CPSR
The mode your should change to is u mode which has the value 0x10
This assume that the current mode is a privileged mode such as supervisor mode
This would happen for instance when the processor is ret – ret code woulud be run in supervisor mode which would then need to switch to usr mode before calling the main routine in your application
You will need to usr MSR and MRS, plus 2 logical operations
A:
mmask EQU0x1f
urmEQU 0x10
#Start of here in supervisor mode
MRSr0, cpsr
BIC r0, r0, #mmask
ORRr0, r0, #urm
MSR cpsr, r0
#End up here in ur mode
