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January 2004s SUPPLY VOLTAGE RANGE:4V TO 5.5V s
TYPICAL PEAK OUTPUT CURRENT:(SOURCE-SINK:1.5A)
s OPERATING FREQUENCY:20TO 500KHz s INHIBIT BLANKING TIME:700ns
s
AUTOMATIC TURN OFF FOR DUTY-CYCLE LESS THAN 14%
s
POSSIBILITY TO OPERATE IN DISCONTINUOUS MODE
DESCRIPTION
STSR30Smart Driver IC provides a high current outputs to properly drive condary Power Mosfets us
ed as Synchronous Rectifier in low output voltage,high efficiency Flyback Converters.From a synchronizing clock input,withdrawn on the condary side of the isolation transformer,the IC generates a driving signal with t dead times with respect to the primary side PWM signal.
The IC operation prevents condary side shoot-through conditions at turn-on of the primary switch providing anticipation in turn-off the output.This smart function is implemented by a fast cycle-after-cycle logic control mechanism,bad on a high frequency oscillator synchronized by the clock signal.This anticipation is externally t through external component.A special Inhibit function,detecting the voltage across the Synchronous FET,allows to shut-off the drive output during discontinuous mode condition.A Disable pin allows turning off the device during no-load condition reducing overall current consumption.
STSR30
SYNCHRONOUS RECTIFIER SMART DRIVER FOR
FLYBACK
BLOCK DIAGRAM
STSR30
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ABSOLUTE MAXIMUM RATINGS (Note 1)
Absolute Maximum Ratings are tho values beyond which damage to the device may occur.Functional operation under the condition is not implied.
(*)A higher positive voltage level can be applied to the pin with a resistor which limits the current flowing into the pin to 10mA maximum
THERMAL DATA
(*)This value is referred to one layer pcb board with
minimum copper connections for the leads.A minimum value of 120°C/W can be obtained improving thermal conductivity of the board
ORDERING CODES
CONNECTION DIAGRAM (top view)
Symbol Parameter
Value Unit V CC DC Input Voltage to SGLGND -0.3to 6V OUT GATE Max Gate Drive Output Voltage -0.3to V CC V DISABLE Max DISABLE Voltage -0.3to V CC V INHIBIT Max INHIBIT Voltage (*)-0.6to V CC V CK Clock Input Voltage Range (*)
-0.3to V CC
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±2KV P TOT Continuous Power Dissipation at T A =105°C SO-8(No heatsink)275mW T STG Storage Temperature Range
-40to +150°C T OP
Operating Junction Temperature Range
-40to +125
°C
Symbol Parameter
SO-8Unit R thj-ca Thermal Resistance Junction-ca 40°C/W R thj-amb
Thermal Resistance Junction-ambient (*)
160(*)
°C/W
TYPE SO-8SO-8(T&R)STSR30
STSR30D
STSR30D-TR
STSR30 PIN DESCRIPTION
Pin N°Symbol Name and Function
1INHIBIT This input enables OUT GATE to work when its voltage is lower than the negative
threshold voltage(V INHIBIT<V H).If V INHIBIT>V H the OUT GATE will be high for a
minimum conduction time(t ON(GATE)).In typical flyback converter application,it is
possible to turn off the synchronous MOSFET when the current through it tends to
rever,allowing discontinuous conduction mode and providing protection to the
converter from eventual sinking current from the load.
A blanking time of700ns allows operation when some voltage ringing is prent
during turn-off of primary switch.
Absolute maximum voltage rating of the pin can be exceeded limiting the current
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flowing into the pin to10mA max.
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2OUT GATE Gate Drive signal for Synchronous MOSFET.Anticipation[t ANT]in turning off
OUT GATE is provided when the clock input goes to low level.
3SGLGND Reference for all the control logic signals.This pin is completely parated from
the PWRGND to prevent eventual disturbances to affect the control logic.
4PWRGND Reference for power signals,this pin carries the full peak currents for the output.
5V CC The supply voltage range from4.5V to5.5V allows applications with logic gate
threshold mosfets.UVLO feature guarantees proper start-up while it avoids
undesirable driving during eventual dropping of the supply voltage.
6DISABLE This pin allows turning off the device completely when kept to low level.In this
condition the IC power consumption is strongly reduced.When this pin goes to
曲线行驶技巧high value,OUT GATE turns to switching again according to the CK signal.
7SETANT The voltage on this pin ts the anticipation in turning off the OUTGATE.It is
假期总结800字possible to choo among three different anticipation times by discrete
partitioning of the supply voltage[ANT].
8CK This input provides synchronization for IC’s operations,being the transitions
between the two output conditions bad on a positive threshold,equal for the
two slopes.A smart internal control logic mechanism using a15MHz internal
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oscillator generates proper anticipation timing at the turn-off of each output.This
feature allows safe turn-off of Synchronous Rectifiers avoiding any eventual
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shoot-through situation on condary side at both transitions.Clock revelation
mechanism makes the operation of STSR30particularly suitable for flyback
adaptors application allowing correct operation during discontinuous mode.
Absolute maximum positive voltage rating of the pin can be exceeded limiting the
current flowing into the pin to10mA max.
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STSR30
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ELECTRICAL CHARACTERISTICS (V CC =5V,CK =100kHz,duty-cycle =50%,V INHIBIT =-200mV,T J =-40to 125°C,C 1=C 2=100nF ceramic,unless otherwi specified.)
Note1:t R is measured between 10%and 90%of the final voltage;t F is measured between 90%and 10%on the initial voltage Note2:Parameter guaranteed by design
Symbol
Parameter
Test Conditions
Min.
Typ.Max.Unit SUPPLY INPUT AND UNDER VOLTAGE LOCK OUT V CC Start Threshold
3.74V Turn OFF Threshold After Start
3.3
3.6I CC Unloaded Supply Current OUT GATE =no load
3.2
4.5mA DISABLE =0V
1550µA GATE DRIVER OUTPUT
OUT GATE Output Low Voltage
I OUTGATE =-200mA 0.20
0.45
V
Output High Voltage
I OUTGATE =200mA 4.30
4.65I OUT Output Source Peak Current T J =25°C 1.5A
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Output Sink Peak Current T J =25°C
1.5R DS(ON)
Output Series Source Resistance 1.75 3.5ΩOutput Series Sink Resistance 1 2.25
t R Ri Time C LOAD =5nF (Note 1)40ns t F Fall Time
C LOA
D =5nF (Note 1)
40ns t P
Clock Propagation Delay to Turn ON of OUT GATE
No Load (Fig.4)25
ns TURN-OFF ANTICIPATION TIME t ANT OUT GATE Turn-off Anticipation Time
(Fig.1)V ANT =0to 1/3V CC ;no load 150ns
V ANT =1/3V CC to 2/3V CC ;no load 225V ANT =2/3V CC to V CC ;no load
300
I SETANT
Leakage Current (Note 2)
-0.1
0.1
µA DISABLE V DP Positive Threshold Voltage V DISABLE >V DP :ON 1.7 2.4
V V DN Negative Threshold Voltage V DISABLE <V DN :OFF
0.8 1.5V V HY Hysteresis Voltage 0.2
V I I Input Current -0.1
0.1
µA INHIBIT (OUT GATE ENABLE)
V H Threshold Voltage T J =25°C
-30
-25mV I H Leakage Current V INHIBIT =+200mV -100
nA V INHIBIT =-200mV 1.5
µA t BL
Blanking Time
V INHIBIT =+200mV
700ns SYNCHRONIZATION INPUT V CK Ri Threshold Voltage
1 1.2V Fall Threshold Voltage
0.60.8D OFF Duty Cycle Shut Down
12
14%
Duty Cycle Turn ON after Shut Down
19
20
STSR30
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Figure 1:TIMING DIAGRAM
Figure 2:STSR30IN FLYBACK CONVERTER SECONDARY SIDE
NOTES
1)Ceramic Capacitors C1and C2must be placed very clo to the IC;2)R1and R2t the anticipation time by partitioning the V CC voltage;3)R3is a pull-up resistor;
4)R5limits the current flowing through diode D2when Freewheeling drain voltage is high;5)D1could be necessary to protect INHIBIT pin from negative voltages.
6)D2could be necessary to protect INHIBIT pin from voltages higher than V CC 7)SGLGND layout trace must not include OUTGATE current
paths.
