This paper is a re-submission of 1570581243 since it is mistakenly withdrawn. And here is the respon:异体受精
Comments to the author (1) Plea explain your rating with a few ntences, 2) indicate any change that should be made to the paper for acceptance, 3) indicate changes that can improve the quality of the paper.) The authors prent a ca study for chip-package-PCB 3D EM simulations and a comparison with measurements.大黄牛
They also propo to replace a pad ring with a PEC block in 3D simulations.
Although the authors insist that the error is less than 1dB, a quick look at the figures clearly shows that this is not true.
It is also not clear why in this extremely simple example a cascade model is not sufficient.
Explanation of the DUT is not sufficiently clear.
English text needs to be improved.
References are not enough.
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# Detailed comments and suggestions to the authors
- English text needs to be improved (e.g. e comments below related to ction 1)
- p.1, col. 1, line 25-26: 'few studies on this topic are reported'. The 'few' studies should be mentioned in the references.
-----> this ntence is deleted since it is not accurate and it involves our motivation of this brief as follows.
In fact, there are only 23 papers mentioning “pad ring” in IEEE Xplore, and a quick glance shows that it ems none talk about its electromagnetic characteristic.
When we are exploring the millimeter-wave IC design, rule of thumb tells it is better not u the pad provides by TSMC (Taiwan Semiconductor Manufacturing Co., ltd.) since the pad by TSMC is sophisticated. While normally the pad for MMIC is a simple lf-drawn rectangle metal.
防溺水的画
手表式手机The figure shows an example of the pad, which is compod of M1, M2, M3, M8 and M9 respectively. Signal runs through M9, where the metal strip is 120-um long (the rectangle bond not included). Besides, this structure includes also diodes and massive vias.
For this device in the example, TSMC does not give a model and from its documents we can find only that it is recommended by TSMC to be equivalent to a capacitor of 100-fF to ground.疑问副词
Obviously, the statement is ok for veral-GHz application. Since our te am’s main business is application below 10-GHz, this simple model worked somewhat in the past.
However, for millimeter-wave application, this model cannot be true. For example, the 120-um long li
ne is coarly estimated to be a 120-pF inductor, which is non-ignorable in millimeter-wave design (ignorable in veral-GHz application). Therefore, EM simulation of the pad ring is necessary.
This structure combines with on-chip pads, involves with package topic (bonding wire), then with PCB (bonding wire must connect to PCB), so it is not easy becau many IC designers do not involve in package and PCB simulation and design.
As the reference [1] says, it is a compound problem (can no longer be simplified and solved using the method in veral-GHz application).
When we are exploring this topic, it is found that rare literature can be found. We think it is already solved somewhere but not published, and maybe the method still needs improvement. For tho who do not solve this problem, the topic is worthy to discusd.
This topic will be popular since it is a ems-not-brilliant-but-important problem and people will arch for the solution, and some innovations are also needed to solve it. The problems talked in the paper are all that we met in the simulation of this chip-package-board system.
The final goal is a methodology that combines PCB, package and on-chip circuit.
stocked
First, for diagnosis of methodology, an independent PCB without devices (the ction II) is validated to confirm the simulation method of PCB.
Second, in the chip-package-PCB system in the ction III, bad on the correct simulation of PCB and abnce of circuit (there is only a simple through line), we can focus on the simulation method of package and pad ring.
qq申诉中心帐号申诉Third, on-chip PDN, ground and circuits can be analyzed and simulated bad on the simulation method of PCB, package and pad ring is validated. Since the on-chip PDN, ground and circuits involve specific circuit design problem, they are discusd in our future work.
- some of the acronyms are not explained (e.g. MMIC and PDK)
- acronyms in the title should be avoided when possible
-----> Already corrected.
- p.1, c. 1, lines 20-22: 'Its structure includes metal layer one to eight for internal ground and power and layer nine for signal in 65-nm CMOS technology.'
醋煎鸡蛋
While the authors were doing a general introduction, they start talking about a specific PCB and the connection is not clear.
-----> Now it is substituted with a general introduction:
It includes multiple metal layers and ESD devices, typically diodes inside which perform the ESD protection.
- p.1, col. 1, lines 20 and 23-24: 'ESD feature' -> maybe 'ESD protection' or similar
- p.1, col. 1, lines 26: 'visa' -> maybe 'vias'
- p.1, col. 2, line 1: 'fusion simulation' -> maybe 'combined simulation'
-----> Already modified.
- p.1, col. 2, lines 2-3: ' the ocnsiderations ... are innovated'?
- from now on I'll stop giving suggestions in English, the authors should improve the text by themlves
-
----> Already modified.
- p.1, col. 2, line 6: 'pure PCB' ?
-----> modified to “PCB without devices”
- p.1, col. 2, line 15: 'consistency rather than performance is the prior concern.' is not clear
-----> modified to “the main concern is consistency between measurement and simulation.”
- p.1, col. 2, line 19: 'they consist well with an error less than 1-dB.' but actually at some freqeuncies the error is almost 3dB in Fig. 2 (e.g. at 21.25GHz),
and probalby larger in Fig. 3, although the figure is not clear becau the legend is missing
-----> now it is limited in S21 and the ntence is modified to “S21 consists well with an error about 2-dB.”
- p.2, col. 1, Fig. 3: legend is missing
- p.2, col. 1, Fig. 4: legend is missing and explanation is not clear
-----> legends are both added.
m odified to “which implies under matched condition, the transition can be improved. To further reduce the intrinsic inrtion loss, optimization can be made [2]”.
- p.2, c. 3, line 7: 'places the line' ?
- p.2, c. 3, Fig. 5: figure is not clear
-----> The figure is updated with a zoom view.
The ntence is modified to “on who right upper corner the through line is drawn”.
- p.2, c. 3, lines 9-10: 'The PCB is designed for another circuits as depicted in Fig.7'. An explanation of the circuit in Fig. 7 is required.
-----> modified to “A test board with the chip is designed for the not-shown circuit of Fig.5as photographed in Fig.7”.
This circuit is not-shown since it is an amplifier for another purpo, not related to the topic of this paper.
- Fig. 9: legend is missing
- p.3, col. 1, lines 4-5: 'they consist well with an error less than 1-dB' but actually in Fig. 10 the error is much higher at some frequencies
-----> a more consistent result has been updated.
and the ntence is modified to “consist well with in the view of curve tendency.”
-----> To better illustrate the chip-package-PCB system, input and output are labelled in the figures. Labels 1 to 6 indicate the signal chain in this DUT system while 1 and 2 show the signal chain for input and output of through line, 3 and 4 for input of not-shown circuit, 5 and 6 for its output.
