18.0-30.0 GHz GaAs Receiver QFN, 7x7 mm
最美的背影
Fundamental High Dynamic Range Receiver Integrated Gain Control
+4.0 dBm Input Third Order Intercept (IIP3)Features
November 2006 - Rev 03-Nov-06
18.0-30.0 GHz GaAs Receiver
QFN, 7x7 mm
Receiver Measurements
November 2006 - Rev 03-Nov-06
I R (d B c )
18
20
22
24
26
28
30
32
34
RF (GHz) [IF=2GHz]
I I P 3 (d B m )
18
20
22
24
26
书香伴我成长作文
28
30
32
34
RF (GHz) [IF=2GHz]
G a i n (d B )
18.0-30.0 GHz GaAs Receiver
QFN, 7x7 mm
Receiver Measurements (cont.)
November 2006 - Rev 03-Nov-06
XR1002-QB, USB Noi Figure (dB) Over Temperature
N F (d B )
18.0-30.0 GHz GaAs Receiver
QFN, 7x7 mm
Physical Dimensions
Pin Designations
(Note: Engineering designator is 30KRP_03A)
Pin Number
Pin Name Pin Function Nominal Value Unit
3GND Ground 4RF IN RF Input
5GND Ground
8VG1&2Gate Bias Voltage -0.5Volt 9VG3Control Bias Voltage
-1.2Volt
10GND Ground 11IF2Out IF2 Output
12GND Ground 17GND Ground 18LO IN LO Input
19GND Ground
23VG4Gate Bias Voltage
-0.8Volt
24GND Ground 25IF1Out IF1 Output
26GND Ground
27
VD1&2Drain Bias Voltage 4.5Volt All Other Pins
NC
Not Connected
November 2006 - Rev 03-Nov-06
18.0-30.0 GHz GaAs Receiver
QFN, 7x7 mm
App Note [1] Biasing - This device is operated with both stages in parallel, and can be biad for lo
w noi performance or high
power performance. Low noi bias is nominally Vd=4.5V, Id=135mA and is the recommended bias condition. More controlled performance will be obtained by parately biasing Vd1 and Vd2 each at 4.5V, 65mA. Power bias may be as high as Vd=5.5V,
Id=270mA with all stages in parallel, or most controlled performance will be obtained by parately biasing Vd1 and Vd2 each at 5.5V, 135mA. Attenuator bias, Vg3, can be adjusted from 0.0 to -1.2V with 0.0V providing maximum attenuation and -1.2V providing minimum attenuation. Image reject mixer bias, Vg4, should nominally be -0.8V to minimize nsitivity of mixer performance to LO level. It is also recommended to u active biasing to keep the currents constant as the RF power and temperature vary; this gives the most reproducible results. Depending on the supply voltage available and the power dissipation constraints, the bias circuit may be a single transistor or a low power operational amplifier, with a low value resistor in ries with the drain supply ud to n the
current. The gate of the pHEMT is controlled to maintain correct drain current and thus drain voltage. The typical gate voltage needed to do this is -0.5V. Typically the gate is protected with Silicon diodes
to limit the applied voltage. Also, make sure to quence the applied voltage to ensure negative gate bias is available before applying the positive drain supply.
MTTF T ab les
Backplate Temperature 55 deg Celsius 75 deg Celsius 95 deg Celsius
Channel Temperature 81 deg Celsius 101 deg Celsius 121 deg Celsius
FITs 1.48E-032.44E-023.04E-01
MTTF Hours 6.77E+114.09E+103.29E+09
从容不迫的意思
Rth -65.0° C/W
-
Bias Conditions: Vd=3.0V, Id=135 mA
Backplate Temperature 55 deg Celsius 75 deg Celsius 95 deg Celsius
小学一年级应用题Channel Temperature 142 deg Celsius 162 deg Celsius 182 deg Celsius
FITs 2.43E+001.87E+011.20E+02
MTTF Hours 4.11E+085.36E+078.35E+06
废物的英文
Rth -58.9° C/W
-Bias Conditions: Vd=5.5V, Id=270 mA
qq名片背景
The numbers were calculated bad on accelerated life test information and thermal model analysis received from the fabricating foundry.
November 2006 - Rev 03-Nov-06
脏的英文
18.0-30.0 GHz GaAs Receiver
QFN, 7x7 mm
App Note [3] USB/LSB Selection -
USB
薛谭学讴读音LSB
For Upper Side Band operation (USB):
November 2006 - Rev 03-Nov-06
