Figure 1: SiC MOSFET Double Pul Tester
the tester is shown in Figure 2. The test fixture contains a
the MOSFET (J6), gate driver (U1), capacitor bank (C1-C9), freewheeling diode (D1), and a tightly integrated two stage current transformer (T1). VDS and VGS can be monitored via BNC connectors (J7 & J10). The intent of the connectors is not to u coaxial cable, but to u a coaxial cable to probe adapter to avoid the need for a probe ground clip. This eliminates the parasitic inductance of the ground clip wire from corrupting the voltage measurement. Drain current is measured using a two stage current transformer consisting of a small 1:10 ferrite first stage transformer and a Pearson Electronics model 2878 current monitor for the cond stage. The resulting scale factor is 1V=100A. Nine polypropylene film capacitors (C1-C9) are ud to provide a low inductance voltage source for the tester. VCC, GND, and –VEE are the input voltage for the gate driver. VCC ts the value for the gate pul high voltage and –VEE ts the value for the gate pul low voltage. Maximum voltage between VCC and –VEE is . The drive pul is applied to the Pul Generator Input BNC connector. A pul of +10 to +12V is recommended to turn on the gate pul. This input is terminated in 50 Ω to match into a 50 Ω coaxial cable. The termination resistors (R3 and R4) have an overall rating of 0.5W maximum so the input pul duty cycle must be appropriately limited (~10%) to avoid burning them out. The indu
ctor is connected across the LOAD LOW and LOAD HIGH terminals.
A recommended inductor value is about 850 µH. This can be realized as an air core inductor constructed by placing a single layer of 107 turns of AWG 18 magnet wire on a length of 4” schedule 40 PVC pipe (OD = 4.5”).
EXTERNAL INDUCTOR CONNECTIONS
VCC
GND
-VEE
Figure 2: SiC MOSFET Double Pul Tester Schematic
出外勤是什么意思A photograph of the top of the tester is shown in Figure 3. The option exists of mounting神农架必去5个景点
the BNC connectors on the top or the bottom of the board. In this ca, the BNC connectors are mounted on the back side to allow a ThermoStream head to be placed over the device under test. (Plea note when installing the BNC connectors on the back side, do not mount the connectors flush to the PCB as a short may result, u a temporary spacer to assist in the installation). All power connections are made using banana plugs and can be inrted from the top or bottom side of the board.
十二生肖谁是老大BNC connectors mounted
Figure 3: SiC MOSFET Double Pul Tester Top View
The bottom side of the tester is shown in Figure 4. Most of the board components are mounted on the back of the board. D1 is installed in a terminal block so it can be removed and replaced with a resistor for probe de-skewing. The jumper shown is the jumper identified in the schematic and is us跷跷板英语
ed for the center pin of the VDS BNC connector. Notice that the gate driver board is mounted bottom side up. The two stage current transformer (T1) is mounted on the bottom. The output of the Pearson current monitor is connected to a SMA-SMA adapter and then to a SMA to BNC bulkhead adapter that feeds through to the top side.
Figure 4: SiC MOSFET Double Pul Tester Bottom View
A detailed view of the first stage current transformer is shown in Figure 5. The transformer consists of 10 turns of AWG 26 solid copper Teflon insulated wire wound around a Ferroxcube TC9.5/4.8/3.2-3E27 ferrite toroid. The center conductor is heavily insulated AWG 22 bus wire suitable for 1.5 kV tests. Figure 6 shows the gate driver board. This board is a modified version of the isolated gate driver board described in the “SiC Isolated Gate Driver” Application Note CPWR-AN10. The board is modified to bypass the DC-DC converters to allow a direct connection to the gate drive power supplies. Notice that the headers are mounted on the top side of the board to allow the board to be mounted bottom side up.
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Figure 5: T1 First Stage Detail
Figure 6: Isolated Gate Driver Board with
DC-DC Converters Removed and Bypasd
T1
Gate Driver Board
Jumper
For accurate measurements, it is very important to de-skew the voltage and current probes to insure that all of the delays are the same. Deskewing the voltage probes is easily done by attaching both probes to a pul generator output and adjusting the channel deskew on the oscilloscope so that both puls are time synchronized. Deskewing the VDS and ID probes can be achieved by removing the inductor and replacing diode D1 with a low inductance 100 Ω resistor. A Caddock MP930-100-1% or equivalent resistor is recommended. Care must be taken during the deskew process to insure that VDD is t to a level below the maximum pul rating of the resistor. The maximum value for the aforementioned resistor is 250V.
A sample waveform of the double pul gate drive is shown in Figure 7. The corresponding sample waveforms of the MOSFET VDS and ID are shown in Figure 8. The pul train consists of two pul
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s with a repetition frequency of about 1-2 Hz. The first pul (~ 22 µc) is ud to build up the current in the inductor. The width is adjusted for the desired test current. When this pul is terminated, ID commutates from the MOSFET to the freewheeling diode. This transition is ud to measure the MOSFET turn-off characteristics. There is a delay of about 3 µc between the first and cond pul. The duration of this delay is t long enough for the voltage and currents to ttle out and might need to be incread if this test fixture is ud to evaluate Si IGBTs to insure adequate time for the tail current to ttle out. The cond narrow pul (~ 2 µc) occurs a few microconds later. Current is commutated from the freewheeling diode back into the MOSFET during this transition and MOSFET turn-on characteristics are measured at this point.
Figure 7: Sample Gate Drive Pul Figure 8: Sample Waveforms
Sample waveforms of VDS and ID at turn-on are shown in Figure 9. Notice the very small amount of current overshoot during turn-on. This is due to the very low amount of stored charge in the SiC JBS diode as compared with a high speed silicon PiN diode. Sample waveforms of VDS and ID at turn-off are shown in Figure 10. Ringing is obrved in both VDS and ID that usually is not obrved with silicon
IGBTs. This is due to the SiC MOSFET’s lack of a current tail.
Figure 9: Turn-On Waveforms Figure 10: Turn-Off Waveforms
The ringing is caud by the output capacitance of the SiC MOSFET resonating with the stray inductance in the high current path. The current tail in the silicon IGBT tends to dampen out this ringing. Plea note that the connector ud to measure VGS is for convenience only to t up the gate pul voltage levels. The actual VGS waveform obrved from that particular point will include the voltage drops of gate bond lead inductance and source bond lead inductance along with the actual VGS voltage. Therefore, when high current puls are being measured, the obrved voltage at this test point will have additional over/
undershoots caud by voltage drops across the aforementioned bond lead inductances.
SiC MOSFET Double Pul Fixture
February 2011
滑稽The bill of materials for the double pul tester is shown in T able 1. The Gerber files can be found at
Table 1: Bill of Materials
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