A continuous-time delta-sigma modulator for 802.11a/b/g WLAN implemented with a hierarchical bottom-up optimization methodology
关于出师表的诗句Tom Eeckelaert ÆRaf Schoofs ÆMichiel Steyaert ÆGeorges Gielen ÆWilly Sann
Received:2April 2007/Revid:27November 2007/Accepted:29January 2008ÓSpringer Science+Business Media,LLC 2008
Abstract This paper prents a 3rd-order continuous-time Delta-Sigma modulator with a resolution of 10bits for a 10MHz signal bandwidth.It is designed in a standard 0.18l m CMOS technology and consumes only 6mW.After the design/lection of the topologies for the integrators,comparator and D/A converters,optimal siz-ing of the complete modulator was ensured by using a hierarchical bottom-up,multi-objective evolutionary design methodology.With this methodology,a t of Pareto-optimal modulator designs is generated by using Pareto-optimal performance solutions of the hierarchically decompod lower-level subblocks.From the generated Pareto-optimal design t,a final optimal design is chon that complies with the specifications for the 802.11a/b/g WLAN standard and has minimal power consumption.
Keywords Continuous-time sigma-delta A/D conversion ÁHigh speed ÁLow power ÁMulti-objective b
ottom-up optimization
1Introduction
At this moment,the standardization of the IEEE 802.11e proposal is in full progress.It will be the latest member of the 802.11WLAN family of standards which are devel-oped to meet the demand for wireless transfer of large amounts of data over a short distance.The driving force behind this evolution is the increasing digital processing speed in the DSP which enables higher bit rates (54Mbit/s).According to the standards,data is transferred in a channel bandwidth of 20MHz by applying OFDM mod-ulation [1].This type of broadband communication requires high-speed building blocks with only moderate dynamic range (9–11bit).The analog-to-digital converter in the front-end of the WLAN receiver is one of the key blocks.
For this type of application,oversampling DR converters are preferred over flash and pipeline converters becau they offer the most economic speed-accuracy trade-off for signal bandwidths up to 50MHz [2].Among the DR converters,discrete-time (DT)modulators are less suitable for high-speed conversions becau ttling time require-ments boost their power consumption.Therefore,they are ud for high-accuracy conversions within lower band-widths like e.
g.in UMTS [3].Besides higher sampling rates,continuous-time (CT)converters on the other hand have additional advantages over DT modulators:no sam-ple-and-hold in front,an inherent anti-aliasing filter and lower thermal noi generation by the filter circuits.This leads to lower power consumption and less chip area.On the down side,CT modulators suffer more from harmonic distortion,matching constraints,loop delay and clock jitter.This paper prents a CT A/D converter at a clock rate of 640MHz.Data conversion is done in baband for frequencies up to 10MHz.Therefore,it can be ud in a
T.Eeckelaert ÁR.Schoofs ÁM.Steyaert ÁG.Gielen (&)ÁW.Sann
Department of Electrical Engineering,ESAT-MICAS,Katholieke Universiteit Leuven,Kasteelpark Arenberg 10,3001Leuven,Belgium
大鹅怎么炖才好吃e-mail:gielen@esat.kuleuven.be T.Eeckelaert
M.Steyaert
e-mail:steyaert@esat.kuleuven.be
明亮的拼音
Analog Integr Circ Sig Process DOI 10.1007/s10470-008-9148-y
潭獐峡quadrature WLAN receiver.The3rd-order,single-bit modulator is designed in a0.18l m triple-well CMOS process with a supply voltage of 1.8V and consumes 6mW.Non-return-to-zero(NRZ)feedback puls are ud to lower the influence of clock jitter.Therefore,an extra feedback coefficient(a4)is introduced[4].The overall architecture is shown in Fig.1.
In the discussion in this paper two complementary parts of the designflow of an electronic system can be distin-guished.On the one side,the design of the topologies for the three integrators,the comparator and the DACs is discusd.And on the other side,for the sizing of the complete modulator system the general multi-objective bottom-up(MOBU)sizing methodology[5,6]is ud.The MOBU methodology was developed in a general way to make it applicable to all kinds of analog/mixed-signal systems.This paper prents thefirst practical results by employing it to the complete design of the CT DR modu-lator of Fig.1.With this methodology a whole t of system designs can be generated which are all Pareto-optimal in the multi-dimensional performance space.The system-level Pareto-optimal design t is generated in a bottom-up way by combining the Pareto-optimal design ts of the different lower-level subblocks.The method-ology also allows to take into account important inter-block constraints during the bottom-up propagation of the designs.As a result,common-mode voltage matching between subquent blocks is guaranteed,as w
ell as output impedance matching between the different DACs and the integrators.After the generation of the t of Pareto-opti-mal modulator designs,the design with the least power consumption that still satisfies the specifications of the 802.11a/b/g WLAN standard is lected.描写老师的段落
This paper is organized as follows.In the next ction the hierarchical MOBU evolutionary optimization algo-rithm is outlined.Section3then prents the design issues that were considered for the different building blocks of the CT DR modulator.In this ction it will also be described how the design,performance and constraint variables of each building block topology are translated tofit the data type of the MOBU optimizer.In addition,becau MOBU works on different abstraction layers,this ction also already provides some design results of the building block designs that were lected for thefinal high-level modulator design that will be discusd in Sect.4.In Sect.4the results of the MOBU optimizer arefirst described and one design is lected that best suits the targeted WLAN specifications.Finally,conclusions are drawn in Sect.5.
2Multi-objective bottom-up design methodology
The existing methodologies for DR modulator design mainly incorporate a top-down design approach[7].High-level simulation and optimization methodologies[8–12] are ud to obtain values fo
r thefilter coefficients or to t boundaries on the lower-level design variables according to high-level performance specifications.After this top-down mapping process,topologies are chon for the different building blocks and the are then sized according to the mapped coefficient values and the design variable bound-aries.The actual sizing of the building block topologies is often still performed manually although commercial auto-matic sizing tools are becoming more and more available [13,14].
With the applied MOBU methodology in this paper, optimization at all levels of abstraction is performed in a bottom-up way.As a result,all the steps described above are combined into this methodology.With the methodology,a complete t of optimal system designs is generated for a particular system architecture and the topologies of its building blocks in a particular miconductor technology. Thus,the results from one MOBU run can be ud in the future for other specifications by just picking a suitable design from the optimal t of designs and becau of the bottom-up generation of the designs,immediately all tran-sistor-level design parameters of the complete system are known.Moreover,MOBU is developed in a general way, making it applicable to all systems,not only to DR ADCs. For an overview of other general synthesis methodologies the reader is referred to[15].More details of the MOBU methodology are described in Sect.2.3.Butfirst some basic concepts of multi-objective optimization is provided.
2.1Multi-objective optimization problem
In classic single-objective design optimization methodol-ogies typically lower or upper boundaries are t on all but one or a few performance characteristics according to the design specifications.If there is more than one objective, they are combined into one cost using a weighted sum of the scaled objectives.The goal is then to meet all the design boundaries and optimize the one cost function,which is often the power consumption in IC [12]).
Analog Integr Circ Sig Process
For the design prented in this paper a novel design methodology is ud that instead optimizes multiple per-formance characteristics at the same time.It is well known that during the design of an analog electronic system,the different performance objectives typically conflict with one another.For i
旺夫相的女人面相nstance,power trades with signal to noi ratio in a converter.So,the solution of the multi-objective optimization methodology will be a t of designs laying on a trade-off front(called Pareto front)in the performance space.A big advantage of this methodology is that the performance trade-off can be generated independently from the application and that the designer does not have to choo weighting coefficients a priori.When the system then has to be designed for a certain application,the analog
designer can pick a point on the a priori generated trade-off front,and immediately all the design variables of all the building blocks are determined.
In a general multi-objective optimization problem the goal is tofind optimal values for the components of a vector function f(x)subject to some constraints e(x): minimize y¼fðxÞ¼½f1ðxÞ;f2ðxÞ;...;f nðxÞ
subject to eðxÞ¼½e1ðxÞ;e2ðxÞ;...;e kðxÞ 0
where x¼½x1;x2;...;x m 2X;
y¼½y1;y2;...;y n 2Y;
ð1Þ
where x is the decision vector,y is the objective vector,X is called the decision space and Y is called the objective space.The k constraints e(x)B0,t restrictions on the decision space.Applied to the electronic design problem, the decision space becomes the design space and the objective space is the performance space.Becau the multiple objective functions almost always conflict with each other,a new definition of optimality has to ud here, which is called Pareto-optimality.
In a t of points,in a multi-dimensional objective space, a point is said to be Pareto-optimal if there is no other point in that t that improves the current point in one objective without deteriorating at least one other objective.
From this definition it is clear that the t of designs that are Pareto-optimal in the performance space forms a boundary surface on the feasible performance space of the electronic system.Taking a step from one point on this surface to an other point on this surface means improving at least one performance characteristic but at the same time also at least one will deteriorate.
2.2Evolutionary algorithm
Evolutionary Algorithms(EA)are well suited to solve multi-objective optimization problems like(1)[16–18]. EAs are stochastic optimization methods designed by analogy with natural evolution.The big diff
erence between classical optimization methods is that they work with a whole t(a population)of solutions(called individuals). In each optimization iteration(called a generation)a new (better)population is created from the old population by first lecting dominant solutions(Darwinian theory of survival of thefittest)and then recombining and mutating them to generate new solutions.Figure2shows the data type of a general EA.An individual is a vector built from chromosomes,and a chromosome is in its turn built from genes.The recombination operator can then be described as a mechanism to exchange chromosomes between two individuals to create two new individuals.This is followed by the mutation operator which stochastically changes the values of the genes.In the next ction,it will be described how this data type is mapped onto a hierarchical decom-position of an electronic system,and how the evolutionary operators offer a means to efficiently explore the design space of the system under design.The details of the implemented algorithm can be found in[5,6].
2.3Hierarchical design space exploration
In this ction the general idea of the MOBU methodology [5,6]is described.Before the methodology can be applied, a hierarchical decomposition of the system under design has to be provided.Figure3shows how the DR modulator depicted in Fig.1is hierarchically decompod in its b
uilding blocks:three integrators,a comparator,and three D/A converters.
After the decomposition,thefirst stage in the MOBU methodology is to generate a t of Pareto-optimal designs for each lowest-level subblock.For this,a multi-objective evolutionary optimization algorithm is ud as described in the previous subction.To extract the performance information needed for the optimizer,a dedicated external circuit simulator can be SPICE).Remark that a Pareto-optimal t is generated for a specific topology,so
Analog Integr Circ Sig Process
designs for building blocks with the same all integrators)can be derived from the same Pareto-optimal t.This is depicted in Fig.4where only Pareto-optimal designs are generated for one cascode integrator topology, one comparator and one DAC topology.
In the cond stage of the MOBU methodology the optimal lowest-level design ts are exploited in a bottom-up way to arch for optimal system-level designs.The design space of the next level up is the‘lection’of a design for each of the subblocks.A‘lected’subblock design is actually pointing to a specific design from the lower-level Pareto-optimal trade-off of that subblock.At higher hierar-chical levels,a simulator with behavioral models can be ud to speed up the external simulations.At this point abstraction is made of the lower-level implementation details.Only the parameters needed to build the behavioral models are extracted from the lected lower-level designs.In our ca, the behavioral model that was ud for the Delta-Sigma modulator,is build from2nd-order models of the different building blocks.In Fig.5,an example of the ud integrator model is depicted.The ud models approximate the ac and transient behavior of the circuits with an accuracy of1–2%. More details on how the model parameters are extracted will be described in the next ction.
The lower-level optimal trade-offs are propagated upwards until the Pareto-optimal trade-offs of the system level(top power versus signal-to-noi ratio(SNR)curve in Fig.4)can be generated.This trade-
off result can be ud by an analog designer to lect afinal design solution that meets the specifications.As a result of the bottom-up generation of the optimal designs,immediately all the lower-level design variables are determined by the lec-tion of the system-level design.
Referring to the data type of an evolutionary algorithm described in the previous ction,for an optimization at the highest hierarchical level,an individual reprents a fully sized system.Each individual contains a chromosome that contains the system design variables(in our design this would be input amplitude,input frequency,oversampling ratio)and a chromosome for each subblock containing one gene that reprents the design‘lected’from the lower level.Recombination of two individuals then means interchanging subblocks from the two individuals to make two new individuals.The mutation operator then means arching new values for the design variables,and shifting to a nearby design point in the lower-level Pareto-optimal ts of designs.
3Circuit implementation
In this ction the design of the topologies of the different subblocks of the modulator are discusd.Regarding the application of the MOBU optimizer discusd in Sect.2, the design and performance variables are also outlined. Becau the MOBU methodology works on different hierarc
椒盐花生米的做法hical abstraction layers,some design results for each building block design that is lected by MOBU in thefinal high-level modulator design(discusd in Sect.4)will also be described.Afinal subction describes how important inter-block constraints can be incorporated in the MOBU methodology.The inter-block on-mode voltage)are very important to ensure proper opera-tion of the building block designs when they are connected to each other in the complete system.
3.1Integrator design
综测In[19],it is demonstrated thatfilters built of GmC inte-grators with source degeneration(GmRC integrator)are more economic than RC integrators for high-speed data conversion with moderate resolution(B11bit).A single-stage folded-cascode topology is chon becau it offers a high DC gain in a power-efficient way since the current in the output branch can be kept low.The schematic of the GmRC integrator is shown at the bottom in the decompo-sition tree of Fig.4.
Analog Integr Circ Sig Process
Degeneration resistors(R deg)are placed at the sources of the input transistors to overcome the nonlinear behavior of their transconductance(g m1)when the input voltage is raid.The cascode transistors(V cas)increa the output impedance of the current transistors(M5).Hence,all the small-signal current is forced toflow through the resistors. As a result,the effective transconductance of the input pair is determined by the degeneration resistors,and the har-monics are suppresd according to the value of the degeneration product(g m1R deg).
The performance variables that were considered as objectives to be optimized by the MOBU optimizer are: minimize power consumption,maximize DC gain,maxi-mize gain-bandwidth(GBW),maximize SNR and maximize signal-to-total-harmonic-distortion(STHD).They are all extracted from Eldo transistor-level simulations.The design variables that were considered as decision variables
lected design
Analog Integr Circ Sig Process
